PLLATINUMSIM-SW — PLLatinum Sim Tool
PLLATINUMSIM-SW is a simulation tool that allows users to create detailed designs and simulations of our PLLatinum™ integrated circuits, which include the LMX series of phase-locked loops (PLLs) and synthesizers.
The LMK61E08 family of ultra-low jitter PLLatinum™ programmable oscillators uses fractional-N frequency synthesizers with integrated VCOs to generate commonly used reference clocks. The output on LMK61E08 can be configured as LVPECL, LVDS, or HCSL. The device features self-start-up from on-chip EEPROM to generate a factory-programmed default output frequency, or the device registers and EEPROM settings are fully programmable in-system through an I2C serial interface. The device provides fine and coarse frequency margining control through an I2C serial interface, making it a digitally-controlled oscillator (DCXO).
The PLL feedback divider can be updated to adjust the output frequency without spikes or glitches in steps of <1ppb using a PFD of 12.5 MHz (R divider=4, doubler disabled) for compatibility with xDSL requirements, or in steps of <5.2 ppb using a PFD of 100 MHz (R divider=1, doubler enabled) for compatibility with broadcast video requirements. The frequency margining features also facilitate system design verification tests (DVT), such as standards compliance and system timing margin testing.
| 類型 | 標題 | 下載最新的英語版本 | 日期 | |||
|---|---|---|---|---|---|---|
| * | 數據表 | LMK61E08 Ultra-Low Jitter Programmable Oscillator With Internal EEPROM 數據表 | PDF | HTML | 2020年 6月 24日 |
如需其他信息或資源,請點擊以下任一標題進入詳情頁面查看(如有)。
LMK61E2EVM 評估模塊提供了一個完整平臺來評估具有集成式 EEPROM 和頻率容限功能的德州儀器 (TI) LMK61E2 超低抖動可編程差動振蕩器的 90fs RMS 抖動性能和可配置性。
LMK61E2EVM 可以用作抖動關鍵型應用的高性能時鐘源,且可以輕松定制為用戶期望的任何頻率和輸出格式。借助板載的 USB 轉 I2C 接口,可通過軟件圖形用戶界面 (GUI) 進行器件配置,且無需提供外部輸入或電源即可運行器件。邊緣發射 SMA 端口可用于訪問 LMK61E2 的差分時鐘輸出,從而使用市售同軸電纜、適配器或平衡-非平衡變壓器(未附帶)連接到測試設備或參考板。
PLLATINUMSIM-SW is a simulation tool that allows users to create detailed designs and simulations of our PLLatinum™ integrated circuits, which include the LMX series of phase-locked loops (PLLs) and synthesizers.
| 封裝 | 引腳 | CAD 符號、封裝和 3D 模型 |
|---|---|---|
| QFM (SIA) | 6 | Ultra Librarian |
推薦產品可能包含與 TI 此產品相關的參數、評估模塊或參考設計。
PLLatinum Sim User's Guide
PLLatinum Sim software manifest
PLLatinum Sim 1.6.9 includes the ability to manually specify points on a phase noise curve (for VCOs or other devices that do not fit the standard three-point model), and as a result the phase noise estimation for many devices which use a BAW VCO is greatly improved. Also includes a bugfix for cascading noise inputs.