PLLATINUMSIM-SW — PLLatinum Sim Tool
PLLATINUMSIM-SW is a simulation tool that allows users to create detailed designs and simulations of our PLLatinum™ integrated circuits, which include the LMX series of phase-locked loops (PLLs) and synthesizers.
The CDCLVD2108 clock buffer distributes two clock inputs (IN0, IN1) to a total of 16 pairs of differential LVDS clock outputs (OUT0, OUT15). Each buffer block consists of one input and 8 LVDS outputs. The inputs can either be LVDS, LVPECL, or LVCMOS.
The CDCLVD2108 is specifically designed for driving 50-
transmission lines. In case of driving the inputs in single ended mode, the appropriate bias voltage (VAC_REF) should be applied to the unused negative input pin.
Using the control pin (EN) outputs can be either disabled or enabled. If the EN pin is left open all outputs are active, if switched to a logical "0" all outputs are disabled (static logical 0), if switched to a logical "1", OUT (8..15) are switched off and OUT (0..7) are active. The part supports a fail safe function. It incorporates an input hysteresis, which prevents random oscillation of the outputs in absence of an input signal.
The device operates in 2.5V supply environment and is characterized from –40°C to 85°C (ambient temperature). The CDCLVD2108 is packaged in small 48-pin, 7-mm × 7-mm QFN package.
| 類型 | 標題 | 下載最新的英語版本 | 日期 | |||
|---|---|---|---|---|---|---|
| * | 數據表 | Dual 1:8 Low Additive Jitter LVDS Buffer 數據表 (Rev. C) | 2010年 12月 21日 |
如需其他信息或資源,請點擊以下任一標題進入詳情頁面查看(如有)。
PLLATINUMSIM-SW is a simulation tool that allows users to create detailed designs and simulations of our PLLatinum™ integrated circuits, which include the LMX series of phase-locked loops (PLLs) and synthesizers.
| 封裝 | 引腳 | CAD 符號、封裝和 3D 模型 |
|---|---|---|
| VQFN (RGZ) | 48 | Ultra Librarian |
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PLLatinum Sim User's Guide
PLLatinum Sim software manifest
PLLatinum Sim 1.6.9 includes the ability to manually specify points on a phase noise curve (for VCOs or other devices that do not fit the standard three-point model), and as a result the phase noise estimation for many devices which use a BAW VCO is greatly improved. Also includes a bugfix for cascading noise inputs.