PLLATINUMSIM-SW — PLLatinum Sim Tool
PLLATINUMSIM-SW is a simulation tool that allows users to create detailed designs and simulations of our PLLatinum™ integrated circuits, which include the LMX series of phase-locked loops (PLLs) and synthesizers.
The CDCLVP1216 is a highly versatile, low additive jitter buffer that can generate 16 copies of LVPECL clock outputs from one of two selectable LVPECL, LVDS, or LVCMOS inputs for a variety of communication applications. It has a maximum clock frequency up to 2 GHz. The CDCLVP1216 features an on-chip multiplexer (MUX) for selecting one of two inputs that can be easily configured solely through a control pin. The overall additive jitter performance is less than 0.1 ps, RMS from 10 kHz to 20 MHz, and overall output skew is as low as 30 ps, making the device a perfect choice for use in demanding applications.
The CDCLVP1216 clock buffer distributes one of two selectable clock inputs (IN0, IN1) to 16 pairs of differential LVPECL clock outputs (OUT0, OUT15) with minimum skew for clock distribution. The CDCLVP1216 can accept two clock sources into an input multiplexer. The inputs can be LVPECL, LVDS, or LVCMOS/LVTTL.
The CDCLVP1216 is specifically designed for driving 50-Ω transmission lines. When driving the inputs in single-ended mode, the LVPECL bias voltage (VAC_REF) should be applied to the unused negative input pin. However, for high-speed performance up to 2 GHz, differential mode is strongly recommended.
The CDCLVP1216 is packaged in a small 48-pin, 7-mm × 7-mm VQFN package and is characterized for operation from 40°C to +85°C.
| 類型 | 標題 | 下載最新的英語版本 | 日期 | |||
|---|---|---|---|---|---|---|
| * | 數據表 | CDCLVP1216 16-LVPECL Output, High-Performance Clock Buffer 數據表 (Rev. F) | PDF | HTML | 2015年 12月 7日 | ||
| EVM 用戶指南 | CDCLVP1216EVM User's Guide | 2009年 5月 27日 |
如需其他信息或資源,請點擊以下任一標題進入詳情頁面查看(如有)。
CDCLVP1216EVM 是用于 CDCLVP1216 的評估模塊。CDCLVP1216 是一款多用途、低附加抖動緩沖器,可從兩個可選 LVPECL(LVDS 或 LVCMOS 輸入)中生成 16 份 LVPECL 時鐘輸出。它的最大時鐘頻率高達 2GHz。低于 0.1ps 的總附加抖動、10kHz 至 20MHz 的 RMS 范圍以及低至 30ps 的總輸出偏移使該器件成為眾多苛刻應用的理想選擇。
PLLATINUMSIM-SW is a simulation tool that allows users to create detailed designs and simulations of our PLLatinum™ integrated circuits, which include the LMX series of phase-locked loops (PLLs) and synthesizers.
| 封裝 | 引腳 | CAD 符號、封裝和 3D 模型 |
|---|---|---|
| VQFN (RGZ) | 48 | Ultra Librarian |
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PLLatinum Sim User's Guide
PLLatinum Sim software manifest
PLLatinum Sim 1.6.9 includes the ability to manually specify points on a phase noise curve (for VCOs or other devices that do not fit the standard three-point model), and as a result the phase noise estimation for many devices which use a BAW VCO is greatly improved. Also includes a bugfix for cascading noise inputs.