PLLATINUMSIM-SW — PLLatinum Sim Tool
PLLATINUMSIM-SW is a simulation tool that allows users to create detailed designs and simulations of our PLLatinum™ integrated circuits, which include the LMX series of phase-locked loops (PLLs) and synthesizers.
The CDCLVP2102 is a highly versatile, low additive jitter buffer that can generate four copies of LVPECL clock outputs from two LVPECL, LVDS, or LVCMOS inputs for a variety of communication applications. It has a maximum clock frequency up to 2 GHz. Each buffer block consists of one input that feeds two LVPECL outputs. The overall additive jitter performance is less than 0.1 ps, RMS from 10 kHz to 20 MHz, and overall output skew is as low as 10 ps, making the device a perfect choice for use in demanding applications.
The CDCLVP2102 clock buffer distributes two clock inputs (IN0, IN1) to four pairs of differential LVPECL clock outputs (OUT0, OUT3) with minimum skew for clock distribution. Each buffer block consists of one input that feeds two LVPECL clock outputs. The inputs can be LVPECL, LVDS, or LVCMOS/LVTTL.
The CDCLVP2102 is specifically designed for driving 50-Ω transmission lines. When driving the inputs in single-ended mode, the LVPECL bias voltage (VAC_REF) should be applied to the unused negative input pin. However, for high-speed performance up to 2 GHz, differential mode is strongly recommended.
The CDCLVP2102 is characterized for operation from 40°C to +85°C and is available in a 3-mm × 3-mm, VQFN-16 package.
| 類型 | 標題 | 下載最新的英語版本 | 日期 | |||
|---|---|---|---|---|---|---|
| * | 數據表 | CDCLVP2102 Four-LVPECL Output, High-Performance Clock Buffer 數據表 (Rev. C) | PDF | HTML | 2013年 10月 25日 | ||
| 用戶指南 | CDCLVP2102 User's Guide | 2009年 7月 9日 |
如需其他信息或資源,請點擊以下任一標題進入詳情頁面查看(如有)。
CDCLVP2102 是一款高性能、低附加相位噪聲時鐘緩沖器。它具有兩個通用輸入緩沖器,支持單端或差動時鐘輸入,并且每個輸入可饋給 2 個 LVPECL 輸出。該器件還具有片上偏壓發生器,它可以為器件輸入提供 LVPECL 共模電壓。此評估模塊 (EVM) 旨在演示 CDCLVP2102 的電性能。這個完全組裝且經過工廠測試的評估板允許對 CDCLVP2102 器件的所有功能進行全面驗證。為達到最佳性能,該評估板配備有 50W SMA 連接器和受控良好的 50W 阻抗微帶傳輸線。
PLLATINUMSIM-SW is a simulation tool that allows users to create detailed designs and simulations of our PLLatinum™ integrated circuits, which include the LMX series of phase-locked loops (PLLs) and synthesizers.
| 封裝 | 引腳 | CAD 符號、封裝和 3D 模型 |
|---|---|---|
| VQFN (RGT) | 16 | Ultra Librarian |
推薦產品可能包含與 TI 此產品相關的參數、評估模塊或參考設計。
PLLatinum Sim User's Guide
PLLatinum Sim software manifest
PLLatinum Sim 1.6.9 includes the ability to manually specify points on a phase noise curve (for VCOs or other devices that do not fit the standard three-point model), and as a result the phase noise estimation for many devices which use a BAW VCO is greatly improved. Also includes a bugfix for cascading noise inputs.