PLLATINUMSIM-SW — PLLatinum Sim Tool
PLLATINUMSIM-SW is a simulation tool that allows users to create detailed designs and simulations of our PLLatinum™ integrated circuits, which include the LMX series of phase-locked loops (PLLs) and synthesizers.
The CDCLVP1102 is a highly versatile, low additive jitter buffer that can generate two copies of LVPECL clock outputs from one LVPECL, LVDS, or LVCMOS input for a variety of communication applications. It has a maximum clock frequency up to 2 GHz. The overall additive jitter performance is less than 0.1 ps, RMS from 10 kHz to 20 MHz, and overall output skew is as low as 10 ps, making the device a perfect choice for use in demanding applications.
The CDCLVP1102 clock buffer distributes a single clock input (IN) to two pairs of differential LVPECL clock outputs (OUT0, OUT1) with minimum skew for clock distribution. The inputs can be LVPECL, LVDS, or LVCMOS/LVTTL.
The CDCLVP1102 is specifically designed for driving 50-Ω transmission lines. When driving the inputs in single-ended mode, the LVPECL bias voltage (VAC_REF) should be applied to the unused negative input pin. However, for high-speed performance up to 2 GHz, differential mode is strongly recommended.
The CDCLVP1102 is characterized for operation from 40°C to 85°C and is available in a QFN-16, 3-mm × 3-mm package.
| 類型 | 標題 | 下載最新的英語版本 | 日期 | |||
|---|---|---|---|---|---|---|
| * | 數據表 | CDCLVP1102 Two-LVPECL Output, High-Performance Clock Buffer 數據表 (Rev. D) | PDF | HTML | 2015年 12月 11日 | ||
| EVM 用戶指南 | CDCLVP1102EVM User's Guide | 2009年 7月 9日 |
如需其他信息或資源,請點擊以下任一標題進入詳情頁面查看(如有)。
CDCLVP1102 是一款高性能、低附加相位噪聲時鐘緩沖器。它具有單個通用輸入緩沖器,支持單端或差動時鐘輸入,并且可饋給 2 個 LVPECL 輸出。該器件還具有片上偏壓發生器,它可以為器件輸入提供 LVPECL 共模電壓。此評估模塊 (EVM) 旨在演示 CDCLVP1102 的電性能。這個完全組裝且經過工廠測試的評估板允許對 CDCLVP1102 器件的所有功能進行全面驗證。為達到最佳性能,該評估板配備有 50W SMA 連接器和受控良好的 50W 阻抗微帶傳輸線。
PLLATINUMSIM-SW is a simulation tool that allows users to create detailed designs and simulations of our PLLatinum™ integrated circuits, which include the LMX series of phase-locked loops (PLLs) and synthesizers.
| 封裝 | 引腳 | CAD 符號、封裝和 3D 模型 |
|---|---|---|
| VQFN (RGT) | 16 | Ultra Librarian |
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PLLatinum Sim User's Guide
PLLatinum Sim software manifest
PLLatinum Sim 1.6.9 includes the ability to manually specify points on a phase noise curve (for VCOs or other devices that do not fit the standard three-point model), and as a result the phase noise estimation for many devices which use a BAW VCO is greatly improved. Also includes a bugfix for cascading noise inputs.