九九久久国产精品九九久久99,四川少妇大战4黑人,国产精品久久自在自线

SNLS779A July 2025 – November 2025 DP83TC815-Q1

PRODUCTION DATA

封裝選項

機械數(shù)據(jù) (封裝 | 引腳)

RHA|36
- MPQF611A

散熱焊盤機械數(shù)據(jù) (封裝 | 引腳)

RHA|36
- QFND711

訂購信息

6.6 Timing Requirements

PARAMETER		TEST CONDITIONS	MIN	NOM	MAX	UNIT
MII TIMING
T1.1	TX_CLK High / Low Time		16	20	24	ns
T1.2	TX_D[3:0], TX_ER, TX_EN Setup to TX_CLK		10			ns
T1.3	TX_D[3:0], TX_ER, TX_EN Hold from TX_CLK		0			ns
T2.1	RX_CLK High / Low Time		16	20	24	ns
T2.2	RX_D[3:0], RX_ER, RX_DV Delay from RX_CLK rising		10		30	ns
RMII LEADER TIMING
T3.1	RMII Leader Clock Period			20		ns
	RMII Leader Clock Duty Cycle		35		65	%
T3.2	TX_D[1:0], TX_ER, TX_EN Setup to RMII Leader Clock		4			ns
T3.3	TX_D[1:0], TX_ER, TX_EN Hold from RMII Leader Clock		2			ns
T3.4	RX_D[1:0], RX_ER, CRS_DV Delay from RMII Leader Clock rising edge		4	10	14	ns
RMII FOLLOWER TIMING
T3.1	Input Reference Clock Period			20		ns
	Reference Clock Duty Cycle		35		65	%
T3.2	TX_D[1:0], TX_ER, TX_EN Setup to XI Clock rising		4			ns
T3.3	TX_D[1:0], TX_ER, TX_EN Hold from XI Clock rising		2			ns
T3.4	RX_D[1:0], RX_ER, CRS_DV Delay from XI Clock rising		4		14	ns
RGMII INPUT TIMING
T_cyc	Clock Cycle Duration	TX_CLK	36	40	44	ns
T_setup(align)	TX_D[3:0], TX_CTRL Setup to TX_CLK (Align Mode)		1	2		ns
T_hold(align)	TX_D[3:0], TX_CTRL Hold from TX_CLK (Align Mode)		1	2		ns
RGMII OUTPUT TIMING
T_skew(align)	RX_D[3:0], RX_CTRL Delay from RX_CLK (Align Mode Enabled)	On PHY Pins	-1.2		1.2	ns
T_setup(shift)	RX_D[3:0], RX_CTRL Delay from RX_CLK (Shift Mode Enabled, default)	On PHY Pins	2			ns
T_cyc	Clock Cycle Duration	RX_CLK	36	40	44	ns
Duty_G	Duty Cycle	RX_CLK	45	50	55	%
SMI TIMING
T4.1	MDC to MDIO (Output) Delay Time	25pF load capacitance	0		40	ns
T4.2	MDIO (Input) to MDC Setup Time		10			ns
T4.3	MDIO (Input) to MDC Hold Time		10			ns
	MDC Frequency			2.5	20	MHz
POWER-UP TIMING
T5.1	Supply ramp time: AVDD, DVDD, VDDIO ⁽¹⁾		0.2		8	ms
T5.1	Supply ramp time: Vsleep ⁽¹⁾		0.4		8	ms
T5.2	Supply ramp delay offset: For all supplies				10	ms
T5.3	XTAL Startup / Settling: Powerup to XI good/stabilized			1.5		ms
T5.4	Oscillator stabilization time from power up				10	ms
	Last Supply power up, stable Clock To Reset Release				10	ms
T5.5	Post power-up to SMI ready: Post Power-up wait time required before MDC preamble can be sent for register access		10			ms
T5.6	Power-up to Strap latch-in				10	ms
T5.7	CLKOUT Startup/Settling: Powerup to CLKOUT good/stabilized				10	ms
T5.8	Power-up to idle stream				10	ms
RESET TIMING (RESET_N)
T6.1	Reset Pulse Width: Miminum Reset pulse width to be able to reset		100			μs
T6.2	Reset to SMI ready: Post reset wait time required before MDC preamble can be sent for register access		1			ms
T6.3	Reset to Strap latch-in: Hardware configuration pins transition to output drivers			80		μs
T6.4	Reset to idle stream				1800	μs
WAKE REQUEST AND WAKE PULSE TIMING
T7.1	Local Wake-Up Pulse Duration		40			μs
T7.2	Local Wake-Up to INH Transition				40	μs
T7.3	Energy-detect-based Wake-Up Pulse Duration				0.7	ms
T7.4	Energy-detect-based Wake-Up to INH Transition				0.7	ms
T7.5	Energy-detect-based Wake-Up to WAKE forwarding pulse				1.4	ms
TRANSMIT LATENCY TIMING
	MII Rising edge TX_CLK with assertion TX_EN to SSD symbol on MD		190		275	ns
	MII Rising edge TX_CLK with assertion TX_EN to SSD symbol on MD	with PTP enabled	170		275	ns
	Follower RMII Rising edge XI clock with assertion TX_EN to SSD symbol on MDI		350		473	ns
	Leader RMII Rising edge clock with assertion TX_EN to SSD symbol on MDI		340		462	ns
	RGMII Rising edge TX_CLK with assertion TX_CTRL to SSD symbol on MDI		340		493	ns
	First symbol of SGMII to SSD symbol on MDI		375		505	ns
RECEIVE LATENCY TIMING
	SSD symbol on MDI to MII Rising edge of RX_CLK with assertion of RX_DV		420		530	ns
	SSD symbol on MDI to MII Rising edge of RX_CLK with assertion of RX_DV	With PTP enabled	450		600	ns
	SSD symbol on MDI to Follower RMII Rising edge of XI clock with assertion of CRS_DV		499		660	ns
	SSD symbol on MDI to Leader RMII Rising edge of Leader clock with assertion of CRS_DV		499		720	ns
	SSD symbol on MDI to Rising edge of RGMII RX_CLK with assertion of RX_CTRL		450		590	ns
	SSD symbol on MDI to first symbol of SGMII		727		884	ns
25 MHz OSCILLATOR REQUIREMENTS
	Frequency Tolerance		-100		+100	ppm
	Rise / Fall Time (10%-90%)				8	ns
	Jitter Tolerance (RMS)				25	ps
	XI Duty Cycle in external clock mode		40		60	%
50 MHz OSCILLATOR REQUIREMENTS
	Frequency			50		MHz
	Frequency Tolerance and Stability Over temperature and aging		–100		100	ppm
	Rise / Fall Time (10% - 90%)				4	ns
	Duty Cycle		35		65	%
25 MHz CRYSTAL REQUIREMENTS
	Frequency			25		MHz
	Frequency Tolerance and Stability Over temperature and aging		–100		100	ppm
	Equivalent Series Resistance				100	Ω
OUTPUT CLOCK TIMING (25 MHz)
	Frequency (PPM)		-100		100	-
	Duty Cycle		40		60	%
	Rise Time				5000	ps
	Fall Time				5000	ps
	Jitter (Short Term)				1000	ps
	Frequency			25		MHz
802.1AS Synchronised Clock
	802.1AS Synchronized Clock Frequency		1		50	MHz
	Duty Cycle		45		55	%
	Jitter (rms)				100	ps
	Jitter (period)				400	ps
	Jitter (cycle to cycle)				300	ps
1pps Output	Synchronization Accuracy (802.1AS Clock source: Internal PLL/NCO DDS) - with optimized settings	Offset Variation across Reset cycles	-30		30	ns
		Jitter for a single reset cycle	-15		15	ns
	Synchronization Accuracy (802.1AS Clock source: recovered Clock @200MHz ) - with optimized settings	Offset Variation across Reset cycles	-30		30	ns
		Jitter for a single reset cycle	-1		1	ns

(1) For supplies with ramp rate longer than 8ms, a RESET pulse is required after the last supply becomes stable.