SNLS779A July 2025 – November 2025 DP83TC815-Q1
PRODUCTION DATA
Digital Loopback loops back data prior to exiting the Digital and entering the AFE. Data received from the MAC on the transmit path is brought through the digital block within the PHY where the data is then routed back to the MAC through the receive path. The DP83TC815-Q1 receive Analog circuitry is configured for isolation to prevent contention.
Write register 0x0868 = 0x085A
Write register 0x04DF = 0x0006
Write register 0x0016 = 0x0104
Write register 0x0619 = 0x1555
Write register 0x0624 = 0x55BF
Data can also be checked internally by reading registers 0x063C, 0x063D, 0x063E
Write register 0x0619 = 0x0557
Write register 0x0624 = 0x55BF
Data generate by the internal PRBS is transmitted over the MDI and the MAC interface.