SNLS779A July 2025 – November 2025 DP83TC815-Q1
PRODUCTION DATA
The DP83TC815-Q1 can be programmed to timestamp an event by monitoring the input signal. The event can be monitored for rising edge, falling edge, or either. The Event Timestamp Unit can monitor up to eight events which can be set to any of the GPIO signal pins. PTP event timestamps are stored in a queue which allows storage of up to eight timestamps. When an event timestamp is available, the device sets the 'Event Ready' bit in the PTP Status Register.
The PTP_ESTS provides detailed information on the available event timestamp, including information on the event number, rise/fall direction, and indication of events missed due to overflow of the device event queue. Event timestamp values must be adjusted by 14ns (3 times period of the IEEE802.1AS reference clock frequency of 250MHz + 2ns) to compensate for input path and synchronization delays. The time value compensated depends on the IEEE802.1AS reference clock frequency. The adjustment time depends on the reference frequency programmed and has to be adjusted based on the clock selected by the host. The Event Timestamp Unit is configured through the PTP Event Configuration Register (PTP_EVNT). External event inputs on the GPIO pins can be monitored and timestamped with the resolution of 4(8) ns. If event interrupts are enabled in the PTP Status Register, an interrupt is generated upon detection of the event.
Each event monitor can be placed in a single-event capture mode. In this mode, the event monitor captures a single event timestamp.