SNLS779A July 2025 – November 2025 DP83TC815-Q1
PRODUCTION DATA
- 1
- 1 Features
- 2 Applications
- 3 Description
- 4 Device Comparison Table
- 5 Pin Configuration and Functions
- 6 Specifications
-
7 Detailed Description
- 7.1 Overview
- 7.2 Functional Block Diagram
- 7.3
Feature Description
- 7.3.1 IEEE802.1AS Features
- 7.3.2
TC10 Sleep Wake-up
- 7.3.2.1 Functions of the PHY for TC10 Support
- 7.3.2.2 Power Supply Networks for Sleep Applications
- 7.3.2.3 Configuration for Non-TC10 Applications
- 7.3.2.4 Miscellaneous Sleep Features
- 7.3.2.5 Fast Wake-up
- 7.3.3 PPM Monitor
- 7.3.4 Clock Dithering
- 7.3.5 Output Slew Control
- 7.3.6 Diagnostic Tool Kit
- 7.3.7 BIST and Loopback Modes
- 7.3.8 Compliance Test Modes
- 7.4 Device Functional Modes
- 7.5 Programming
- 8 Register Maps
- 9 Application and Implementation
- 10Device and Documentation Support
- 11Revision History
- 12Mechanical, Packaging, and Orderable Information
7.3.1 IEEE802.1AS Features
The DP83TC815-Q1 integrates IEEE 1588v2/802.1AS timestamping and other additional hardware engines to offer highly accurate synchronization with synchronization jitter of up to ±15ns (with options to reduce to up to ±1ns for point-to-point connections).
The DP83TC815-Q1 is also capable of providing a high quality time synchronized clock signal to achieve system level synchronization for ADAS sensor data synchronization, Corner RADAR Chirp synchronization, 1 pps signal for LiDAR, V2X, etc.
Figure 7-1 DP83TC815-Q1 Example PTP System ApplicationThe PTP implementation consists of the following major function blocks:
- IEEE802.1AS Clock: This block provides an adjustable clock that is used as the time source for all PTP timestamp related functions.
- IEEE802.1AS PTP Timestamp: This block provides timestamping and packet modification functions.
- IEEE802.1AS Clock Events and GPIOs: This block provides clock events and GPIO functions for enabling timestamping of input events and for outputting clock comparison-based outputs/interrupt status.
- IEEE802.1AS Interrupt: This block provides interrupt generation, masking and status indication functions.
- IEEE802.1AS Registers: This block contains all configuration, control and status registers related information.
The range of register address used for IEEE802.1AS PTP implementation are listed below:
| ADDRESS |
|---|
| 0x0D00 to 0x0D0A |
| 0x0D10 to 0x0D1D |
| 0x0D20 to 0x0D2B |
| 0x0D30 to 0x0D3F |
| 0x0D40 to 0x0D4F |
| 0x0D50 to 0x0D54 |
| 0x0DE0, 0x0DF0 |
IEEE802.1AS provides a time synchronization protocol, often referred to as the Precision Time Protocol (PTP), which synchronizes time across an Ethernet network. DP83TC815-Q1 supports IEEE802.1AS enabled Ethernet applications by providing hardware support for three time-critical elements.
- IEEE802.1AS synchronized clock generation
- Packet timestamps for clock synchronization
- Event triggering and timestamping through GPIO