SNLS779A July 2025 – November 2025 DP83TC815-Q1
PRODUCTION DATA
- 1
- 1 Features
- 2 Applications
- 3 Description
- 4 Device Comparison Table
- 5 Pin Configuration and Functions
- 6 Specifications
-
7 Detailed Description
- 7.1 Overview
- 7.2 Functional Block Diagram
- 7.3
Feature Description
- 7.3.1 IEEE802.1AS Features
- 7.3.2
TC10 Sleep Wake-up
- 7.3.2.1 Functions of the PHY for TC10 Support
- 7.3.2.2 Power Supply Networks for Sleep Applications
- 7.3.2.3 Configuration for Non-TC10 Applications
- 7.3.2.4 Miscellaneous Sleep Features
- 7.3.2.5 Fast Wake-up
- 7.3.3 PPM Monitor
- 7.3.4 Clock Dithering
- 7.3.5 Output Slew Control
- 7.3.6 Diagnostic Tool Kit
- 7.3.7 BIST and Loopback Modes
- 7.3.8 Compliance Test Modes
- 7.4 Device Functional Modes
- 7.5 Programming
- 8 Register Maps
- 9 Application and Implementation
- 10Device and Documentation Support
- 11Revision History
- 12Mechanical, Packaging, and Orderable Information
7.3.4 Clock Dithering
To reduce the emissions from clock and data switching, DP83TC815-Q1 supports clock dithering on internal system clocks and MAC interface clock, data pins. The frequency of clocks is modulated with time to spread out the signal energy and reduce emissions. Figure 7-9 shows the example of dithered clock frequency using triangular and sawtooth profile, with time.
Figure 7-9 Clock Dithering Frequency
ProfilesDithering can be enabled and disabled using register 0x05A8. Separate options are available for enabling dithering of internal core clocks and MAC interface.
To tweak the EMC performance, the following dithering options are available on DP83TC815-Q1
- Dithering Profile:
- Triangular and Sawtooth profiles are available
- Dithering Modulation
Period: Cycle time across which average of Δ(f) is 0.
- EMC performance has higher improvement with higher modulation period.
- Dithering Maximum
Frequency Offset (Δ(f)): Configure maximum ratio of frequency offset
w.r.t average frequency of the clock
- EMC performance has higher improvement with higher Δ(f)
The above options are available from programming using registers 0x05A1 and 0x05A8
Impact of Dithering MAC Interface:
Dithering of clocks results in shrinkage and elongation of clock period of MAC interface signals over the modulation period. This causes the Inter-Packet Gap between packets to shrink or elongate. The output clock period of MAC interface reference clock also shrinks or elongates. Table 7-11 shows the comparison of Inter-Packet Gap and RGMII MAC interface period.
| S.NO | Δf/f | DITHER MODULATION TIME | 25MHz CYCLE SLIPs | IPG VARIATION | 25MHz CLOCK PERIOD VARIATION |
|---|---|---|---|---|---|
| Sawtooth/Triangular | |||||
| 1 | 1% | 8.33 us | ±1 | ±0.5 byte | ±0.4ns |
| 2 | 2% | 8.33 us | ±2 | ±1 byte | ±0.8ns |
| 3 | 2% | 16.66 us | ±4 | ±2 byte | ±0.8ns |
When MAC interface dithering is enabled, the compliance of Ethernet MAC to IPG shrinkage and Clock period variation must be made sure.