SNLS779A July 2025 – November 2025 DP83TC815-Q1
PRODUCTION DATA
- 1
- 1 Features
- 2 Applications
- 3 Description
- 4 Device Comparison Table
- 5 Pin Configuration and Functions
- 6 Specifications
-
7 Detailed Description
- 7.1 Overview
- 7.2 Functional Block Diagram
- 7.3
Feature Description
- 7.3.1 IEEE802.1AS Features
- 7.3.2
TC10 Sleep Wake-up
- 7.3.2.1 Functions of the PHY for TC10 Support
- 7.3.2.2 Power Supply Networks for Sleep Applications
- 7.3.2.3 Configuration for Non-TC10 Applications
- 7.3.2.4 Miscellaneous Sleep Features
- 7.3.2.5 Fast Wake-up
- 7.3.3 PPM Monitor
- 7.3.4 Clock Dithering
- 7.3.5 Output Slew Control
- 7.3.6 Diagnostic Tool Kit
- 7.3.7 BIST and Loopback Modes
- 7.3.8 Compliance Test Modes
- 7.4 Device Functional Modes
- 7.5 Programming
- 8 Register Maps
- 9 Application and Implementation
- 10Device and Documentation Support
- 11Revision History
- 12Mechanical, Packaging, and Orderable Information
7.5.1 Strap Configuration
The DP83TC815-Q1 uses functional pins as strap options to place the device into specific modes of operation. The values of these pins are sampled at power up and hardware reset (through either the RESET pin or register access). Some strap pins support 3 levels and some strap pins support 2 levels, which are described in greater detail below. PHY address straps, RX_DV/RX_CTRL and RX_ER, are 3-level straps while all other straps are two levels. Configuration of the device can be done through strapping or through serial management interface.
Because strap pins are functional pins after reset is deasserted, they must not be connected directly to VDDIO or VDDMAC or GND. Either pullup resistors, pulldown resistors, or both are required for proper operation.
When using VDDMAC and VDDIO separately, it is important to connect strap resistors to the correct voltage rail. Each pin voltage domain is listed in the table below.
Figure 7-24 Strap Circuit
Rpulldn value is included in the Electrical Characteristics table of the data sheet.
| MODE3 | IDEAL RH (k?) (VDDIO = 3.3V)1 | IDEAL RH (k?) (VDDIO = 2.5V)2 | IDEAL RH (k?) (VDDIO = 1.8V)1 |
|---|---|---|---|
| 1 | OPEN | OPEN | OPEN |
| 2 | 13 | 12 | 4 |
| 3 | 4.5 | 2 | 0.8 |
- Strap resistors with 10% tolerance.
- Strap resistors with 1% tolerance.
- RL is optional and can be added if voltage on bootstrap pins needs to be adjusted.
- Strap resistors with up to 10% tolerance can be used.
- To gain more margin in customer application for 1.8V VDDIO, either 2.1k? ±10% pullup can be used or resistor accuracy of 2.49k? resistor can be limited to 1%.
The following table describes the PHY configuration bootstraps:
| PIN NAME | PIN NO. | DOMAIN | DEFAULT MODE | STRAP FUNCTION | DESCRIPTION | ||
|---|---|---|---|---|---|---|---|
| RX_DV/RX_CTRL | 15 | VDDMAC | 1 | MODE | PHY_AD[0] | PHY_AD[2] | PHY_AD: PHY Address ID |
| 1 | 0 | 0 | |||||
| 2 | 0 | 1 | |||||
| 3 | 1 | 1 | |||||
| RX_ER | 14 | VDDMAC | 1 | MODE | PHY_AD[1] | PHY_AD[3] | PHY_AD: PHY Address ID |
| 1 | 0 | 0 | |||||
| 2 | 0 | 1 | |||||
| 3 | 1 | 1 | |||||
| CLKOUT | 16 | VDDMAC | 1 | MODE | AUTO | AUTO: Autonomous Disable. This is a duplicate strap for LED_1. If CLKOUT pin is configured as LED_1 pin then the AUTOstrap functionality also moves to the CLKOUT pin. | |
| 1 | 0 | ||||||
| 2 | 1 | ||||||
| RX_D0 | 26 | VDDMAC | 1 | MODE | MAC[0] | MAC: MAC Interface Selection | |
| 1 | 0 | ||||||
| 2 | 1 | ||||||
| RX_D1 | 25 | VDDMAC | 1 | MODE | MAC[1] | MAC: MAC Interface Selection | |
| 1 | 0 | ||||||
| 2 | 1 | ||||||
| RX_D2 | 24 | VDDMAC | 1 | MODE | MAC[2] | MAC: MAC Interface Selection | |
| 1 | 0 | ||||||
| 2 | 1 | ||||||
| RX_D3 | 23 | VDDMAC | 1 | MODE | CLKOUT_PIN | CLKOUT_PIN: This strap determines which pin is used for output clock. | |
| 1 | 0 | ||||||
| 2 | 1 | ||||||
| LED_0 | 35 | VDDIO | 1 | MODE | MS | MS: 100BASE-T1 Leader & 100BASE-T1 Follower
Selection | |
| 1 | 0 | ||||||
| 2 | 1 | ||||||
| LED_1 | 6 | VDDIO | 1 | MODE | AUTO | AUTO: Autonomous Disable This is the default strap pin for controlling AUTO feature. If this pin is configured as CLKOUT, the AUTO feature moves to pin 16. | |
| 1 | 0 | ||||||
| 2 | 1 | ||||||
| GPIO_4 | 19 | VDDMAC | 1 | MODE | RESERVED | Reserved. Leave unconnected. | |
| 1 | 0 | ||||||
| 2 | 1 | ||||||
| RX_CLK | 27 | VDDMAC | 1 | MODE | TC10 | TC10 Disable: This pin strap decides whether TC10 is enabled or disabled | |
| 1 | 0 | ||||||
| 2 | 1 | ||||||
RX_D3 strap pin has a special functionality of controlling the output status of CLKOUT (pin 16) and LED_1 (pin 6). The Table 7-42 table below shows how pin 16 and pin 6 are affected by RX_D3 strap status. Note that RX_D3 option only changes the pin functionality but not the voltage domains. Pin 16 is always in VDDMAC domain and Pin 6 is always in VDDIO domain. If VDDIO and VDDMAC are at separate voltage levels, it must be ensured that pin 16 and pin 6 are strapped to the respective voltage domains.
In clock output daisy chain applications, if VDDMAC and VDDIO are at different voltages then clock output must be routed to pin 6. Internal oscillator of the DP83TC815-Q1 operates in the VDDIO domain, so clock output must also be used on the pin in VDDIO domain, that is, pin 6. In clock output daisy chain applications where VDDMAC and VDDIO are same, this requirement can be ignored. This requirement can also be ignored in applications where clock output is not being used.
| CLKOUT_PIN | DESCRIPTION |
|---|---|
| 0 | Pin 16 is Clock output, Pin 6 is LED_1 pin. AUTO is controlled by straps on pin 6. |
| 1 | Pin 6 is Clock output, Pin 16 is LED_1 pin. AUTO is controlled by straps on pin 16. |
| MS | DESCRIPTION |
|---|---|
| 0 | 100BASE-T1 Follower Configuration |
| 1 | 100BASE-T1 Leader Configuration |
| AUTO | DESCRIPTION |
|---|---|
| 0 | Autonomous Mode, PHY able to establish link after power-up |
| 1 | Managed Mode, PHY must be allowed to establish link after power-up based on register write |
| TC10 | DESCRIPTION |
|---|---|
| 0 | TC10 is enabled |
| 1 | TC10 is disabled. This strap prevents PHY from transition to sleep mode. |
| MAC[2] | MAC[1] | MAC[0] | DESCRIPTION |
|---|---|---|---|
| 0 | 0 | 0 | SGMII (4-wire)(1) |
| 0 | 0 | 1 | MII |
| 0 | 1 | 0 | RMII Follower(2) |
| 0 | 1 | 1 | RMII Leader |
| 1 | 0 | 0 | RGMII (Align Mode) |
| 1 | 0 | 1 | RGMII (TX Internal Delay Mode) |
| 1 | 1 | 0 | RGMII (TX and RX Internal Delay Mode) |
| 1 | 1 | 1 | RGMII (RX Internal Delay Mode) |
| PHY_AD[3:0] | RX_CTRL STRAP MODE | RX_ER STRAP MODE | DESCRIPTION Section 7.5.1 |
|---|---|---|---|
| 0000 | 1 | 1 | PHY Address: b0000 (0x0) |
| 0001 | - | - | NA |
| 0010 | - | - | NA |
| 0011 | - | - | NA |
| 0100 | 2 | 1 | PHY Address: b0100 (0x4) |
| 0101 | 3 | 1 | PHY Address: b0101 (0x5) |
| 0110 | - | - | NA |
| 0111 | - | - | NA |
| 1000 | 1 | 2 | PHY Address: b1000 (0x8) |
| 1001 | - | - | NA |
| 1010 | 1 | 3 | PHY Address: b1010 (0xA) |
| 1011 | - | - | NA |
| 1100 | 2 | 2 | PHY Address: b1010 (0xC) |
| 1101 | 3 | 2 | PHY Address: b1011 (0xD) |
| 1110 | 2 | 3 | PHY Address: b1110 (0xE) |
| 1111 | 3 | 3 | PHY Address: b1111 (0xF) |