SNLS779A July 2025 – November 2025 DP83TC815-Q1
PRODUCTION DATA
The DP83TC815-Q1 provides a synchronized clock output signal for use by external devices. The output clock signal can be any frequency generated from reference clock divided by n, where n is an integer in the range of 2 to 255. This provides nominal frequencies from 125MHz down to 980.4kHz if the reference clock used is 250MHz.
The synchronized clock output is only supported when PTP Reference Clock used is PTP_PLL. The frequency of PTP_PLL is programmable.
The clock output signal frequency is controlled by the PTP_COC register. The output GPIO is controlled by the CLKOUT_MUX_CTL register. The output clock signal is generated using the rate information in the PTP_RATEH and PTP_RATEL registers and is therefore frequency accurate to the IEEE802.1AS clock time of the device. Note that any step adjustment in the IEEE802.1AS clock time cannot be accurately be represented on the 802.1AS clock output signal.