SNLS779A July 2025 – November 2025 DP83TC815-Q1
PRODUCTION DATA
- 1
- 1 Features
- 2 Applications
- 3 Description
- 4 Device Comparison Table
- 5 Pin Configuration and Functions
- 6 Specifications
-
7 Detailed Description
- 7.1 Overview
- 7.2 Functional Block Diagram
- 7.3
Feature Description
- 7.3.1 IEEE802.1AS Features
- 7.3.2
TC10 Sleep Wake-up
- 7.3.2.1 Functions of the PHY for TC10 Support
- 7.3.2.2 Power Supply Networks for Sleep Applications
- 7.3.2.3 Configuration for Non-TC10 Applications
- 7.3.2.4 Miscellaneous Sleep Features
- 7.3.2.5 Fast Wake-up
- 7.3.3 PPM Monitor
- 7.3.4 Clock Dithering
- 7.3.5 Output Slew Control
- 7.3.6 Diagnostic Tool Kit
- 7.3.7 BIST and Loopback Modes
- 7.3.8 Compliance Test Modes
- 7.4 Device Functional Modes
- 7.5 Programming
- 8 Register Maps
- 9 Application and Implementation
- 10Device and Documentation Support
- 11Revision History
- 12Mechanical, Packaging, and Orderable Information
7.3.1.1.2 PTP Synchronized Clock (Wall Clock)
The PTP time clock in DP83TC815-Q1 is a readable or writable time source for all IEEE802.1AS PTP related functions. PTP clock is a high accuracy oscillator and a counter that represents time in seconds and nanoseconds.
The clock consists of Seconds (32–bit field) and Nanoseconds (30–bit field). When the nanoseconds counter reaches 1 x 109, the nanoseconds counter reverts to zero and the seconds counter increments by 1. Additionally, a Fractional Nanoseconds (sub nanosecond - units of 2-32 ns) counter for time adjustment is available. PTP_RATE_DIR controls whether the device operates at a higher or lower frequency than the reference clock. The clock counter increment per cycle varies depending on the reference clock used and is equal to the period (in ns) corresponding to the PTP reference clock. A Frac PLL is used to generate non-integer synchronized clock output. Use of Frac PLL eliminates need for external VCXO.
Figure 7-2 PTP Timestamping -
ClockThe clock does not support negative time values. If negative time is required in the system, the host software has to make conversions from the PHY clock time to actual time.
The clock also does not support the upper 16-bits of the seconds field as defined by the specification (Version 2 specifies a 48-bit seconds field). If the upper 16-bits value is required to be greater than 0, it has to be handled by host software. The rollover of the seconds field only occurs every 136 years, minimizing burden to host software.