SLVSBD1B December 2012 – August 2025 TPS65175
PRODUCTION DATA
- 1
- 1 Features
- 2 Applications
- 3 Description
- 4 Pin Configurations
- 5 Ordering Information #GUID-A66BA10C-7D19-4133-842F-4CC0C2AD52C6/SLVSAP8211
- 6 Specifications
- 7 DAC Range Summary
-
8 Detailed Description
- 8.1 Boost Converter (VDD)
- 8.2 Boost Converter Design Procedure
- 8.3 Buck Converter (VCC)
- 8.4 Buck Converter Design Procedure
- 8.5 Synchronous Buck Converter (HVDD)
- 8.6 Synchronous Buck Converter Design Procedure
- 8.7 Positive Charge Pump Controller (VGH) and Temperature Compensation
- 8.8 Positive Charge Pump Design Procedure
- 8.9 VGH Temperature Compensation
- 8.10 Negative Charge Pump (VGL)
- 8.11 Negative Charge Pump Design Procedure
- 8.12 P-Vcom Voltage and Gain (VCOM)
- 8.13 P-Vcom Design Procedure
- 8.14 P-Vcom Temperature Compensation
- 8.15 Gamma Buffer (GMA1-GMA6)
- 8.16 Level Shifters
- 8.17 State Machine
- 8.18 GCLK
- 8.19 MCLK
- 8.20 GST
- 8.21 E/O
- 8.22 Reverse
- 8.23 VGH_F and VGH_R
- 8.24 VST
- 8.25 RESET
- 8.26 EVEN and ODD
- 8.27 Abnormal Operation
- 8.28 CLK1 to CLK6
- 8.29 Gate Voltage Shaping
- 8.30 Power Supply Sequencing (CLK1-CLK6, VST, RESET)
- 8.31 Power Supply Sequencing (EVEN, ODD)
- 8.32 Power Supply Sequencing (VGH_F, VGH_R)
- 101
- 8.33 Typical Applications
- 9 APPENDIX – I2C INTERFACE
- 10Detailed Description
- 11Register Map
- 12DAC Registers
- 13Electrostatic Discharge Caution
- 14Revision History
- 15Mechanical, Packaging, and Orderable Information
4 Pin Configurations
Table 4-1 Pin Descriptions
| PIN | I/O1 | DESCRIPTION | |
|---|---|---|---|
| NAME | NO. | ||
| REVERSE | 1 | I | REVERSE input pin |
| GCLK | 2 | I | GCLK input pin |
| MCLK | 3 | I | MCLK input pin |
| GST | 4 | I | GST input pin |
| E/O | 5 | I | E/O input pin |
| GND | 6 | Ground pin | |
| VGL | 7 | I | Negative charge pump (VGL) output voltage sense pin |
| SWN | 8 | I/O | Negative charge pump (VGL) switch pin |
| CTRLN | 9 | O | Negative charge pump (VGL) base drive signal pin |
| RST | 10 | O | Reset generator open drain output pin |
| OUTB | 11 | I | Buck converter (VCC) output voltage sense pin |
| SWB | 12 | I/O | Buck converter (VCC) switch pin |
| AGND | 13, exposed pad | Analog ground pin. Connect this pin to the PowerPAD?. | |
| PVINB | 14 | I | Buck converter (VCC) input supply pin |
| AVIN | 15 | I | Internal regulator supply pin |
| PVINH | 16 | I | Synchronous buck converter (HVDD) power input pin |
| SWH | 17 | I/O | Synchronous buck converter (HVDD) switch pin |
| OUTH | 18 | I | Synchronous buck converter (HVDD) output voltage sense pin |
| PGNDH | 19 | Synchronous buck converter (HVDD) power ground pin | |
| SCL | 20 | I/O | I2C clock pin |
| SDA | 21 | I/O | I2C data pin |
| VL | 22 | O | Internal regulator output pin. Connect an output capacitor to this pin |
| TCOMP | 23 | I | Temperature compensation input pin. Connect the thermistor / pull-up resistor network to this pin |
| PGND | 24 | Boost converter (VDD) power ground pin | |
| SW | 25,26 | I/O | Boost converter (VDD) switch pin |
| SWI | 27 | I | Isolation switch input pin. The SWI pin is connected to the internal overvoltage protection comparator of the boost converter |
| SWO | 28 | O | Isolation switch output pin (VDD) |
| SS | 29 | O | Boost converter (VDD) soft-start pin. Connect a capacitor to this pin if a soft-start is needed. Open = no soft-start. |
| COMP | 30 | I/O | Boost converter (VDD) compensation pin |
| GMA1 | 31 | O | Gamma buffer 1 output pin. DAC output |
| GMA2 | 32 | O | Gamma buffer 2 output pin. DAC output |
| GMA3 | 33 | O | Gamma buffer 3 output pin. DAC output |
| GMA4 | 34 | O | Gamma buffer 4 output pin. DAC output |
| GMA5 | 35 | O | Gamma buffer 5 output pin. DAC output |
| GMA6 | 36 | O | Gamma buffer 6 output pin. DAC output |
| VGND | 37 | Ground pin for the VCOM Op-Amp | |
| VCOM | 38 | O | Operational amplifier (VCOM) output pin |
| VCOM_FB | 39 | I | Operational amplifier (VCOM) inverting pin. Connect the panel feedback to this pin |
| CTRLP | 40 | O | Positive charge pump (VGH) base drive signal pin |
| SWP | 41 | I/O | Positive charge pump (VGH) switch pin |
| VGH | 42 | I | Positive charge pump (VGH) output voltage sense pin and level shifters supply pin |
| VGH_E/O | 43 | I | EVEN / ODD channels supply pin |
| RESET | 44 | O | RESET output pin |
| VST | 45 | O | VST output pin |
| EVEN | 46 | O | EVEN output pin |
| ODD | 47 | O | ODD output pin |
| VGH_F | 48 | O | VGH_F output pin |
| VGH_R | 49 | O | VGH_R output pin |
| CLK6 | 50 | O | CLK6 output pin |
| CLK5 | 51 | O | CLK5 output pin |
| CLK4 | 52 | O | CLK4 output pin |
| CLK3 | 53 | O | CLK3 output pin |
| CLK2 | 54 | O | CLK2 output pin |
| CLK1 | 55 | O | CLK1 output pin |
| RE | 56 | O | Gate shaping resistor connection pin |
- I = input, O = output
- All other pins functions are the same for TPS65175 and TPS65175A.