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SLVSBD1B December 2012 – August 2025 TPS65175

PRODUCTION DATA

封裝選項

機械數據 (封裝 | 引腳)

RSH|56
- MPQF191C

散熱焊盤機械數據 (封裝 | 引腳)

RSH|56
- QFND099F

6.4 Electrical Characteristics

AV_IN = PV_INB = PV_INH = 12V, V_DD = 16V, HV_DD = 8V , V_CC = 3.3V for TPS65175 / V_CC = 1.8V for TPS65175A , V_{GH_LT} = 30V, V_{GH_HT} = 28V, V_GL = –5V, V_COM = 7.5V, T_A = –40°C to 85°C, typical values are at T_A = 25°C (unless otherwise noted). Values in bold are guaranteed through test, design or correlations.

PARAMETER		TEST CONDITIONS	MIN	TYP	MAX	UNIT
POWER SUPPLY
V_IN	Input voltage range		8.6		14.7	V
I_{Q_AVIN}	Supply quiescent current AVIN	Device not switching		2.0	4.0	mA
I_{Q_PVINB}	Supply quiescent current PVINB	Device not switching		0.1	1.0	mA
I_{Q_PVINH}	Supply quiescent current PVINH	Device not switching		1.5	2.5	mA
I_{Q_SWI}	Supply quiescent current SWI	Device not switching		7.3	12	mA
I_{Q_VGH}	Supply quiescent current VGH	E/O, GCLK, GST, MCLK, REVERSE = 0 V		0.4	0.6	mA
I_{Q_VGH_E/O}	Supply quiescent current VGH_E/O	E/O, GCLK, GST, MCLK, REVERSE = 0 V		0.06	0.1	mA
I_{Q_VGL}	Negative supply current	E/O, GCLK, GST, MCLK, REVERSE = 0 V		0.13	0.25	mA
LCD BIAS MISCELLANEOUS
V_UVLO	Undervoltage lockout	AV_IN rising	8.3	8.6	8.9	V
V_UVLO	Undervoltage lockout hysteresis		0.3	0.8	1.3	V
T_SD	Thermal shutdown	T_J rising	130	138	150	°C
T_HYS	Thermal shutdown hysteresis	T_J falling	8.5	9	10	°C
LOGIC SIGNAL SCL, SDA
V_IH	High level input voltage SCL, SDA	Input rising, AV_IN = 8.6 V to 14.7 V	0.65*V_CC			V
V_IL	Low level input voltage SCL, SDA	Input falling, AV_IN = 8.6 V to 14.7 V			0.3 x V_CC	V
INTERNAL OSCILLATOR
f_OSC	Low switching frequency for the boost, the buck converter and the charge pumps		600	750	900	kHz
f_OSC	High switching frequency for the boost and the buck converter		1.2	1.5	1.8	MHz
INTERNAL REGULATOR
V_L⁽²⁾	Internal regulator	No load	4.8	5.0	5.2	V
V_L⁽²⁾	Internal regulator	5 mA current	4.8	5.0	5.2	V
BOOST CONVERTER [V_DD]
V_{DD_ACC}	Output voltage accuracy	V_DD default value	–2%	16	2%	V
r_DS(on)	N-MOSFET on-resistance - TPS65175	I_SW = current limit		90	165	mΩ
r_DS(on)	N-MOSFET on-resistance - TPS65175A	I_SW = current limit		100	179	mΩ
I_LIM	N-MOSFET current limit		3.5	4.3	5.2	A
I_SS	Soft-start current	V_SS = 1.230 V	7	10	13	μA
	Line regulation	AV_IN = 8.6 V to 14.7 V, I_OUT = 700 mA		0.002		%/V
	Load regulation	I_OUT = 0 A to 1 A		0.066		%/A
ISOLATION SWITCH
r_DS(on)ISO	Isolation MOSFET on-resistance	I_SWI = 1 A		100	180	mΩ
I_{SC_ISO}	Short circuit current limit	V_SWI = 12 V, V_SWO = 0 V	100	200	300	mA
BUCK CONVERTER [V_CC]
V_{CC_ACC}	Output voltage accuracy	V_CC default value TPS65175	–3%	3.3	3%	V
V_{CC_ACC}	Output voltage accuracy	V_CC default value TPS65175A	–3%	1.8	3%	V
r_DS(on)	Switch on-resistance	I_SWB = current limit		180	300	mΩ
I_LIM	Switch current limit		2.6	3.4	4.2	A
	Line regulation	V_IN = AV_IN = PV_INB = 8.6 V to 14.7 V I_CC = 200 mA		0.001		%/V
	Load regulation	I_CC = 0 A to 800 mA		0.033		%/A
SYNCHRONOUS BUCK CONVERTER [HV_DD]
HV_{DD_ACC}	Output voltage accuracy	HV_DD default value	–2%	8	2%	V
r_DS(on)	MOSFET on-resistance	I_SBW3 = current limit		320	480	mΩ
I_LIM	Switch current limit – source		0.9	1.3	1.7	A
I_LIM	Switch current limit – sink		–0.9	–1.3	–1.7	A
f_SWH	Switching frequency synchronous buck converter		1.2	1.5	1.8	MHz
	Line regulation	AV_IN = PV_INH = 8.6 V to 14.7 V I_OUT = ±300 mA		0.003		%/V
	Load regulation	I_OUT = –500 mA to 500 mA		0.007		%/A
POSITIVE CHARGE PUMP CONTROLLER [V_GH]
V_{GH_LT_ACC}	Output voltage accuracy	V_{GH_LT} default value	–3%	30	3%	V
V_{GH_HT_ACC}	Output voltage accuracy	V_{GH_HT} default value	–3%	28	3%	V
I_{CTRLP_SC}	Base current during short circuit	VGH = GND	40	55	75	μA
I_{CTRLP_max}	Maximum base current		1	1.6	2	mA
	Line regulation	AV_IN = 8.6 V to 14.7 V, I_GH = 50 mA		0.004		%/V
	Load regulation	I_GH = 0 A to 100 mA		0.414		%/A
NEGATIVE CHARGE PUMP CONTROLLER [V_GL]
V_GL	Output voltage accuracy	V_GL default value	–3%	–5	3%	V
I_{CTRLN_SC}	Base current during short circuit	VGL = GND	200	320	440	μA
I_{CTRLN_max}	Maximum base current		1	1.6	3	mA
	Line regulation	AV_IN = 8.6 V to 14.7 V, I_GL = 50 mA		0.001		%/V
	Load regulation	I_GL = 0 A to 100 mA		0.817		%/A
GAMMA BUFFER [GMA]
I_O	Continuous output current		10	30		mA
V_OH1	Output voltage swing high GMA1,2,3	I_OUT = 10mA	V_DD–0.7	V_DD–0.5		V
V_OL1	Output voltage swing low GMA1,2,3	I_OUT = 10mA		HV_DD+0.5	HV_DD+0.7	V
V_OH2	Output voltage swing high GMA4,5,6	I_OUT = 10mA	HV_DD–0.7	HV_DD–0.5		V
V_OL2	Output voltage swing low GMA4,5,6	I_OUT = 10mA		0.5	0.7	V
INL_max	Maximum integral nonlinearity			±0.6		LSB
DNL_max	Maximum differential nonlinearity			±0.3		LSB
RESET GENERATOR [ RST]⁽¹⁾
V_RST(ON)	Low voltage level	I_RST(ON) = 1 mA			0.4	V
I_{LEAK_ RST}	Leakage current	V_RST(ON) = V_CC = 3.3 V			2	μA
P-VCOM [VCOM]
V_COM	Output voltage accuracy	V_COM default value	–2%	7.5	2%	V
BW	Unity gain -3dB bandwidth	V_CM = 7.5 V, V_IN = 63 mVpp	55	75	95	MHz
AV_OL	Open loop gain	V_CM = 7.5 V	100	120	140	dB
CMRR	Common-Mode Rejection Ratio	V_CM = 7.5 V	95	110	125	dB
PSRR	Power Supply Rejection Ratio	V_CM = 7.5 V, V_DD = 12.7 V to 19 V	80	110	140	dB
SR	Slew rate rising	Unity gain, V_{COM_FB} = 7.5 V ± 2 V_PP	23	45	80	V/μs
SR	Slew rate falling	Unity gain, V_{COM_FB} = 7.5 V ± 2 V_PP	25	45	80	V/μs
r_DS(on)	High-side output resistance	I_OUT = 10 mA, sourcing, V_COM = 9.5 V, V_NEG = 7.5 V		20	40	Ω
r_DS(on)	Low-side output resistance	I_OUT = 10 mA, sinking, V_COM = 7.5 V, V_NEG = 9.5 V		2	10	Ω
I_PK	Peak output current sourcing	Unity gain, VCOM = GND	400	550		mA
I_PK	Peak output current sinking	Unity gain, VCOM = SWO	400	550		mA
LEVEL SHIFTERS MISCELLANEOUS
UVLO	Undervoltage lockout rising	V_GH rising	5.0	9.2	11	V
UVLO	Undervoltage lockout falling	V_GH falling	2.0	3.5	5.0	V
LEVEL SHIFTERS INPUT SIGNALS (E/O, GCLK, GST, MCLK, REVERSE)
V_IH	High level input voltage E/O, GCLK, GST, MCLK, REVERSE	V_GH = 17 V to 34 V, T_A = 25°C ~ 85°C	1.25			V
V_IH	High level input voltage E/O, GCLK, GST, MCLK, REVERSE	V_GH = 17 V to 34 V, T_A = -40°C ~ 85°C	1.30			V
V_IL	Low level input voltage E/O, GCLK, GST, MCLK, REVERSE	V_GH = 17 V to 34 V			0.75	V
I_IN	Input current	E/O, GCLK, GST, MCLK = 0 V			±100	nA
		E/O, GCLK, GST, MCLK = 3.3 V			±100	nA
		REVERSE = 3.3 V	24	33	44	μA
R_PULL-DOWN	REVERSE pin internal pull-down resistor		75	100	135	kΩ
LEVEL SHIFTERS OUTPUTS (CLK1 to CLK6)
r_DS(on)	High side ON resistance	I_OUT = 10 mA, sourcing (high side)		12	30	Ω
r_DS(on)	Low side ON resistance	I_OUT = 10 mA, sinking (low side)		7	15	Ω
t_PLH	GCLK rising edge propagation delay	GCLK rising edge to CLK rising edge, C_OUT = 300 pF		50	100	ns
t_PHL	MCLK falling edge propagation delay	MCLK falling edge to CLK falling edge, C_OUT = 300 pF		50	100	ns
LEVEL SHIFTERS OUTPUTS (EVEN, ODD, RESET, VGH_F, VGH_R, VST)
r_DS(on)	High side ON resistance	I_OUT = 10 mA, sourcing (high side)		35	80	Ω
r_DS(on)	Low side ON resistance	I_OUT = 10 mA, sinking (low side)		16	40	Ω
t_PLH	GST rising edge propagation delay	GST rising edge to VST rising edge, C_OUT = 300 pF		60	120	ns
t_PLH	GST rising edge propagation delay	GST rising edge to RESET rising edge, C_OUT = 300 pF		60	120	ns
t_PHL	GST falling edge propagation delay	GST falling edge to VST falling edge, C_OUT = 300 pF		60	120	ns
t_PHL	GST falling edge propagation delay	GST falling edge to RESET falling edge, C_OUT = 300 pF		60	120	ns
t_PLH	E/O rising edge propagation delay	E/O rising edge to ODD falling edge, C_OUT = 300 pF		60	120	ns
t_PLH	E/O rising edge propagation delay	E/O rising edge to EVEN falling edge, C_OUT = 300 pF		60	120	ns
t_PHL	E/O falling edge propagation delay	E/O falling edge to ODD rising edge, C_OUT = 300 pF		60	120	ns
t_PHL	E/O falling edge propagation delay	E/O falling edge to EVEN rising edge, C_OUT = 300 pF		60	120	ns
t_SU	E/O set-up time during abnormal operation	E/O to GST rising edge		5	30	ns
t_PLH	REVERSE rising edge propagation delay	REVERSE rising edge to VGH_F falling edge, C_OUT = 300 pF		60	120	ns
t_PHL	GST rising edge propagation delay	GST rising edge to VGH_R falling edge, C_OUT = 300 pF		60	120	ns
t₁₂	REVERSE dead time	VGH_F falling edge to VGH_R rising edge, C_OUT = 300 pF	20	500	1000	ns
t₁₃	REVERSE dead time	VGH_R falling edge to VGH_F rising edge, C_OUT = 300 pF	20	500	1000	ns
GATE VOLTAGE SHAPING (RE)
r_DS(on)	Gate shaping resistance	Measured between active CLK channel and RE at 10 mA		70	140	Ω
t_PHL	MCLK rising edge propagation delay	MCLK rising edge to CLK falling edge, C_OUT = 300 pF		65	100	ns
I_LEAK	Gate shaping leakage current	Measured between RE and GND	-10		10	μA

(1) External pull-up resistor to be chosen so that the current flowing into RST pin when active (V_RST = 0 V) is below I_RST(ON) = 1 mA.

(2) The V_L regulator can supply 5 mA externally