SLVSBD1B December 2012 – August 2025 TPS65175
PRODUCTION DATA
- 1
- 1 Features
- 2 Applications
- 3 Description
- 4 Pin Configurations
- 5 Ordering Information #GUID-A66BA10C-7D19-4133-842F-4CC0C2AD52C6/SLVSAP8211
- 6 Specifications
- 7 DAC Range Summary
-
8 Detailed Description
- 8.1 Boost Converter (VDD)
- 8.2 Boost Converter Design Procedure
- 8.3 Buck Converter (VCC)
- 8.4 Buck Converter Design Procedure
- 8.5 Synchronous Buck Converter (HVDD)
- 8.6 Synchronous Buck Converter Design Procedure
- 8.7 Positive Charge Pump Controller (VGH) and Temperature Compensation
- 8.8 Positive Charge Pump Design Procedure
- 8.9 VGH Temperature Compensation
- 8.10 Negative Charge Pump (VGL)
- 8.11 Negative Charge Pump Design Procedure
- 8.12 P-Vcom Voltage and Gain (VCOM)
- 8.13 P-Vcom Design Procedure
- 8.14 P-Vcom Temperature Compensation
- 8.15 Gamma Buffer (GMA1-GMA6)
- 8.16 Level Shifters
- 8.17 State Machine
- 8.18 GCLK
- 8.19 MCLK
- 8.20 GST
- 8.21 E/O
- 8.22 Reverse
- 8.23 VGH_F and VGH_R
- 8.24 VST
- 8.25 RESET
- 8.26 EVEN and ODD
- 8.27 Abnormal Operation
- 8.28 CLK1 to CLK6
- 8.29 Gate Voltage Shaping
- 8.30 Power Supply Sequencing (CLK1-CLK6, VST, RESET)
- 8.31 Power Supply Sequencing (EVEN, ODD)
- 8.32 Power Supply Sequencing (VGH_F, VGH_R)
- 101
- 8.33 Typical Applications
- 9 APPENDIX – I2C INTERFACE
- 10Detailed Description
- 11Register Map
- 12DAC Registers
- 13Electrostatic Discharge Caution
- 14Revision History
- 15Mechanical, Packaging, and Orderable Information
8.29 Gate Voltage Shaping
The clock outputs CLK1 to CLK6 support gate voltage shaping, which can help reduce image flickering in certain applications. A simplified block diagram of one of the clock channels is shown in Figure 8-14.
Figure 8-14 CLK Output Stage- On the rising edge of the GCLK, the active channel's Q1 is enabled and its Q2 disabled; the output goes to VGH.
- Gate voltage shaping starts on the rising edge of MCLK, which disables Q1 and enables Q3. The LCD panel's pixel and storage capacitor now discharge through Q3 at a rate determined by the external resistor RE (see Figure 8-15).
- On the falling edge of MCLK, Q3 is disabled and Q2 enabled; the output goes to VGL.
Figure 8-15 Gate Shaping Timing Diagram