SLVSBD1B December 2012 – August 2025 TPS65175
PRODUCTION DATA
The clock outputs CLK1 to CLK6 support gate voltage shaping, which can help reduce image flickering in certain applications. A simplified block diagram of one of the clock channels is shown in Figure 8-14.
Figure 8-14 CLK Output Stage
Figure 8-15 Gate Shaping Timing Diagram