When AVIN > 8.6 V the device is enabled, VL goes into regulation and the
RST signal is set 'low' and DLY0 starts.
When the DLY0 has passed, the buck converter (VCC) starts up.
When PGB is reached, DLY1 starts.
When DLY1 has passed,
RST is released and the negative charge pump controller (VGL) starts.
When PGN is reached and DLY2 has passed, the boost converter (VDD) and the synchronous buck converter (HVDD) start. The Gamma Buffer outputs as well as the VCOM output rise at a ratio metric rate of VDD.
When PG is reached and DLY3 has passed, the positive charge pump controller (VGH) starts.
When VGH > 9.2 V, the Level Shifter block is enabled.