ZHCSJN2B May 2019 – January 2021 DS90UH941AS-Q1
PRODUCTION DATA
WriteI2C (0x01,0x08) //Disable DSI
WriteI2C (0x1E,0x01) //Select FPD-Link III Port 0
WriteI2C (0x1E,0x04) //Use I2D ID+1 for FPD-Link III Port 1 register access
WriteI2C (0x1E,0x01) //Select FPD-Link III Port 0
WriteI2C (0x03,0x9A) //Enable I2C_PASSTHROUGH, FPD-Link III Port 0
WriteI2C (0x1E,0x02) //Select FPD-Link III Port 1
WriteI2C (0x03,0x9A) //Enable I2C_PASSTHROUGH, FPD-Link III Port 1
WriteI2C (0x1E,0x01) //Select FPD-Link III Port 0
WriteI2C (0x40,0x05) //Select DSI Port 0 digital registers
WriteI2C (0x41,0x21) //Select DSI_CONFIG_1 register
WriteI2C (0x42,0x60) //Set DSI_VS_POLARITY=DSI_HS_POLARITY=1
WriteI2C (0x1E,0x02) //Select FPD-Link III Port 1
WriteI2C (0x40,0x09) //Select DSI Port 1 digital registers
WriteI2C (0x41,0x21) //Select DSI_CONFIG_1 register
WriteI2C (0x42,0x60) //Set DSI_VS_POLARITY=DSI_HS_POLARITY=1
WriteI2C (0x1E,0x01) //Select FPD-Link III Port 0
WriteI2C (0x5B,0x05) //Force Independent 2:2 mode
WriteI2C (0x4F,0x8C) //Set DSI_CONTINUOUS_CLOCK, 4 lanes, DSI Port 0
WriteI2C (0x1E,0x01) //Select FPD-Link III Port 0
WriteI2C (0x40,0x04) //Select DSI Port 0 digital registers
WriteI2C (0x41,0x05) //Select DPHY_SKIP_TIMING register
WriteI2C (0x42,0x1E) //Write TSKIP_CNT value for 315 MHz DSI clock (1080p, PCLK = 105 MHz)
WriteI2C (0x1E,0x02) //Select FPD-Link III Port 1
WriteI2C (0x4F,0x8C) //Set DSI_CONTINUOUS_CLOCK, 4 lanes, DSI Port 1
WriteI2C (0x1E,0x01) //Select FPD-Link III Port 0
WriteI2C (0x40,0x08) //Select DSI Port 1 digital registers
WriteI2C (0x41,0x05) //Select DPHY_SKIP_TIMING register
WriteI2C (0x42,0x14) //Write TSKIP_CNT value for 225 MHz DSI clock (720p, PCLK = 75 MHz)
WriteI2C (0x01,0x00) //Enable DSI