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ZHCSGZ6A October 2017 – February 2025 TPS6508700

PRODUCTION DATA

封裝選項(xiàng)

請(qǐng)參考 PDF 數(shù)據(jù)表獲取器件具體的封裝圖。

機(jī)械數(shù)據(jù) (封裝 | 引腳)

RSK|64

散熱焊盤機(jī)械數(shù)據(jù) (封裝 | 引腳)

RSK|64
- QFND521A

訂購信息

6.9.1 Register Map Summary

Table 6-7 lists the memory-mapped registers for the TPS6508700. All register offset addresses not listed in Table 6-7 should be considered as reserved locations and the register contents should not be modified.

Table 6-7 Register Map Summary

Offset	Acronym	Short Description	Section
1h	DEVICEID	Device ID code indicating revision	Go
2h	IRQ	Interrupt statuses	Go
3h	IRQ_MASK	Interrupt masking	Go
4h	PMICSTAT	PMIC temperature indicator	Go
5h	SHUTDNSRC	Shutdown root cause indicator bits	Go
21h	BUCK2CTRL	BUCK2 decay control and voltage select	Go
22h	BUCK3DECAY	BUCK3 decay control	Go
23h	BUCK3VID	BUCK3 voltage select	Go
24h	BUCK3SLPCTRL	BUCK3 voltage select for SLEEP state	Go
25h	BUCK4CTRL	BUCK4 control	Go
26h	BUCK5CTRL	BUCK5 control	Go
27h	BUCK6CTRL	BUCK6 control	Go
28h	LDOA2CTRL	LDOA2 control	Go
29h	LDOA3CTRL	LDOA3 control	Go
40h	DISCHCTRL1	Discharge resistors for each rail control	Go
41h	DISCHCTRL2	Discharge resistors for each rail control	Go
42h	DISCHCTRL3	Discharge resistors for each rail control	Go
43h	PG_DELAY1	System Power Good on GPO3 (if GPO3 is programmed to be system PG)	Go
91h	FORCESHUTDN	Software force shutdown	Go
93h	BUCK2SLPCTRL	BUCK2 voltage select for SLEEP state	Go
94h	BUCK4VID	BUCK4 voltage select	Go
95h	BUCK4SLPVID	BUCK4 voltage select for SLEEP state	Go
96h	BUCK5VID	BUCK5 voltage select	Go
97h	BUCK5SLPVID	BUCK5 voltage select for SLEEP state	Go
98h	BUCK6VID	BUCK6 voltage select	Go
99h	BUCK6SLPVID	BUCK6 voltage select for SLEEP state	Go
9Ah	LDOA2VID	LDOA2 voltage select	Go
9Bh	LDOA3VID	LDOA3 voltage select	Go
9Ch	BUCK123CTRL	BUCK1, 2, and 3 disable and PFM/PWM mode control	Go
9Dh	PG_DELAY2	System Power Good on GPO1, 2, and 4 (if GPOs are programmed to be system PG)	Go
9Fh	SWVTT_DIS	SWs and VTT I²C disable bits	Go
A0h	I2C_RAIL_EN1	I²C enable control of individual rails	Go
A1h	I2C_RAIL_EN2/GPOCTRL	I²C enable control of individual rails and I²C controlled GPOs, high or low	Go
A2h	PWR_FAULT_MASK1	Power fault masking for individual rails	Go
A3h	PWR_FAULT_MASK2	Power fault masking for individual rails	Go
A4h	GPO1PG_CTRL1	Power good tree control for GPO1	Go
A5h	GPO1PG_CTRL2	Power good tree control for GPO1	Go
A6h	GPO4PG_CTRL1	Power good tree control for GPO4	Go
A7h	GPO4PG_CTRL2	Power good tree control for GPO4	Go
A8h	GPO2PG_CTRL1	Power good tree control for GPO2	Go
A9h	GPO2PG_CTRL2	Power good tree control for GPO2	Go
AAh	GPO3PG_CTRL1	Power good tree control for GPO3	Go
ABh	GPO3PG_CTRL2	Power good tree control for GPO3	Go
ACh	MISCSYSPG	Power Good tree control with CTL3 and CTL6 for GPO	Go
AEh	LDOA1CTRL	LDOA1 control for discharge, voltage selection, and enable	Go
B0h	PG_STATUS1	Power Good statuses for individual rails	Go
B1h	PG_STATUS2	Power Good statuses for individual rails	Go
B2h	PWR_FAULT_STATUS1	Power fault statuses for individual rails	Go
B3h	PWR_FAULT_STATUS2	Power fault statuses for individual rails	Go
B4h	TEMPCRIT	Critical temperature indicators	Go
B5h	TEMPHOT	Hot temperature indicators	Go
B6h	OC_STATUS	Overcurrent fault status	Go

Complex bit access types are encoded to fit into small table cells. Table 6-8 shows the codes that are used for access types in this section.

Table 6-8 Access Type Codes

Access Type	Code	Description
Read Type
R	R	Read
Write Type
W	W	Write
Reset or Default Value
-nh		Value after reset or the default value