ZHCSGZ6A October 2017 – February 2025 TPS6508700
PRODUCTION DATA
請參考 PDF 數據表獲取器件具體的封裝圖。
BUCK123CTRL is shown in Figure 6-43 and described in Table 6-37.
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| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| SPARE | BUCK3_MODE | BUCK2_MODE | BUCK1_MODE | BUCK3_DIS | BUCK2_DIS | BUCK1_DIS | |
| R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-1h | R/W-1h | R/W-1h | |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 7-6 | SPARE | R/W | 0h | Spare bits. |
| 5 | BUCK3_MODE | R/W | 0h | This field sets the BUCK3 regulator operating mode. 0h = Automatic mode 1h = Forced PWM mode |
| 4 | BUCK2_MODE | R/W | 0h | This field sets the BUCK2 regulator operating mode. 0h = Automatic mode 1h = Forced PWM mode |
| 3 | BUCK1_MODE | R/W | 0h | This field sets the BUCK1 regulator operating mode. 0h = Automatic mode 1h = Forced PWM mode |
| 2 | BUCK3_DIS | R/W | 1h | BUCK3 disable bit. Writing 0 to this bit forces BUCK3 to turn off regardless of any control input pin (CTL1–CTL6) status. 0h = Disable 1h = Enable |
| 1 | BUCK2_DIS | R/W | 1h | BUCK2 disable bit. Writing 0 to this bit forces BUCK2 to turn off regardless of any control input pin (CTL1–CTL6) status. 0h = Disable 1h = Enable |
| 0 | BUCK1_DIS | R/W | 1h | BUCK1 disable bit. Writing 0 to this bit forces BUCK1 to turn off regardless of any control input pin (CTL1–CTL6) status. 0h = Disable 1h = Enable |