ZHCSGZ6A October 2017 – February 2025 TPS6508700
PRODUCTION DATA
請參考 PDF 數據表獲取器件具體的封裝圖。
DISCHCTRL1 is shown in Figure 6-29 and described in Table 6-23.
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All xx_DISCHG[1:0] bits internally set to 0h whenever the corresponding VR is enabled.
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| BUCK4_DISCHG[1:0] | BUCK3_DISCHG[1:0] | BUCK2_DISCHG[1:0] | BUCK1_DISCHG[1:0] | ||||
| R/W-1h | R/W-1h | R/W-1h | R/W-1h | ||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 7-6 | BUCK4_DISCHG[1:0] | R/W | 1h | BUCK4 discharge resistance 0h = no discharge 1h = 100 Ω 2h = 200 Ω 3h = 500 Ω |
| 5-4 | BUCK3_DISCHG[1:0] | R/W | 1h | BUCK3 discharge resistance 0h = no discharge 1h = 100 Ω 2h = 200 Ω 3h = 500 Ω |
| 3-2 | BUCK2_DISCHG[1:0] | R/W | 1h | BUCK2 discharge resistance 0h = no discharge 1h = 100 Ω 2h = 200 Ω 3h = 500 Ω |
| 1-0 | BUCK1_DISCHG[1:0] | R/W | 1h | BUCK1 discharge resistance 0h = no discharge 1h = 100 Ω 2h = 200 Ω 3h = 500 Ω |