ZHCSGZ6A October 2017 – February 2025 TPS6508700
PRODUCTION DATA
請參考 PDF 數(shù)據(jù)表獲取器件具體的封裝圖。
PG_DELAY1 is shown in Figure 6-32 and described in Table 6-26.
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Programmable power good delay for GPO3 pin, measured from the moment when all VRs assigned to GPO3 pin reach their regulation range to power good assertion. This register is optional as the PMIC can be programmed for system PG, level shifter or I2C controller GPO.
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | GPO3_PG_DELAY[2:0] | ||||||
| R-0h | R/W-0h | ||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 7-3 | RESERVED | R | 0h | |
| 2-0 | GPO3_PG_DELAY[2:0] | R/W | 0h | Programmable delay power good or level shifter for GPO3 pin. Measured from the moment when all rails grouped to this pin reach their regulation range. All values have ±10% variation. 0h = 2.5 ms 1h = 5 ms 2h = 10 ms 3h = 15 ms 4h = 20 ms 5h = 50 ms 6h = 75 ms 7h = 100 ms |