ZHCSGZ6A October 2017 – February 2025 TPS6508700
PRODUCTION DATA
請參考 PDF 數據表獲取器件具體的封裝圖。
| PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
|---|---|---|---|---|---|---|
| BUCK3, BUCK4, BUCK5 | ||||||
| VIN | Power input voltage | 4.5 | 5 | 5.5 | V | |
| VOUT | DC output voltage VID range and options | VID step size = 25mV, BUCKx_VID[6:0] progresses from 0000001b to 1111111b | 0.425 | 3.575 | V | |
| BUCK3 output voltage default | Set by BUCK3_VID[6:0], 25mV step size | 1.8 | V | |||
| BUCK4 output voltage default | Set by BUCK4_VID[6:0], 25mV step size | 0.8 | V | |||
| BUCK5 output voltage default | Set by BUCK5_VID[6:0], 25mV step size | 1.8 | V | |||
| DC output voltage accuracy | VOUT = 1, 1.2,
1.35, 1.5, 1.8, 2.5, 3.3V, IOUT = 1.5A | –2% | 2% | |||
| VOUT = 1, 1.2,
1.35, 1.5, 1.8, 2.5, 3.3 V, IOUT = 100mA | –2.5% | 2.5% | ||||
| Total output voltage accuracy (DC plus ripple) in DCM | IOUT = 10mA, VOUT ≤ 1V | –30 | 40 | mV | ||
| SR(VOUT) | Output DVS slew rate | 5 | 6.25 | mV/μs | ||
| IOUT | Continuous DC output current | 3 | A | |||
| IIND_LIM | HSD FET current limit | 4.3 | 7 | A | ||
| IQ | Quiescent current | VIN = 5V, VOUT = 1V | 35 | μA | ||
| ΔVOUT/ΔVIN | Line regulation | VOUT = 1, 1.2,
1.35, 1.5, 1.8, 2.5, 3.3V, IOUT = 1.5A | –0.5% | 0.5% | ||
| ΔVOUT/ΔIOUT | Load regulation | VIN = 5V,
VOUT = 1, 1.2, 1.35, 1.5, 1.8, 2.5, 3.3V, IOUT = 0A to 3A, referenced to VOUT at IOUT = 1.5A | –0.2% | 2% | ||
| VTH_PG | Power good deassertion threshold in percentage of target VOUT | VOUT rising | 108% | |||
| VOUT falling | 92% | |||||
| VTH_HYS_PG | Power good reassertion hysteresis entering back into VTH_PG | VOUT rising or falling | 3% | |||
| RDIS | Output auto-discharge resistance | BUCKx_DIS[1:0] = 01b | 100 | Ω | ||
| BUCKx_DIS[1:0] = 10b | 200 | |||||
| BUCKx_DIS[1:0] = 11b | 500 | |||||