ZHCSGZ6A October 2017 – February 2025 TPS6508700
PRODUCTION DATA
- 1
- 1 特性
- 2 應用
- 3 說明
- 4 Pin Configuration and Functions
-
5 Specifications
- 5.1 Absolute Maximum Ratings
- 5.2 ESD Ratings
- 5.3 Recommended Operating Conditions
- 5.4 Thermal Information
- 5.5 Electrical Characteristics: Total Current Consumption
- 5.6 Electrical Characteristics: Reference and Monitoring System
- 5.7 Electrical Characteristics: Buck Controllers
- 5.8 Electrical Characteristics: Synchronous Buck Converters
- 5.9 Electrical Characteristics: LDOs
- 5.10 Electrical Characteristics: Load Switches
- 5.11 Digital Signals: I2C Interface
- 5.12 Digital Input Signals (CTLx)
- 5.13 Digital Output Signals (IRQB, GPOx)
- 5.14 Timing Requirements
- 5.15 Switching Characteristics
- 5.16 Typical Characteristics
-
6 Detailed Description
- 6.1 Overview
- 6.2 Functional Block Diagram
- 6.3 SMPS Voltage Regulators
- 6.4 LDO Regulators and Load Switches
- 6.5 Power Good Information (PGOOD or PG) and GPO Pins
- 6.6 Power Sequencing and Voltage-Rail Control
- 6.7 Device Functional Modes
- 6.8 I2C Interface
- 6.9
Register Maps
- 6.9.1 Register Map Summary
- 6.9.2 DEVICEID: PMIC Device and Revision ID Register (offset = 1h) [reset = 10h]
- 6.9.3 IRQ: PMIC Interrupt Register (offset = 2h) [reset = 0h]
- 6.9.4 IRQ_MASK: PMIC Interrupt Mask Register (offset = 3h) [reset = FFh]
- 6.9.5 PMICSTAT: PMIC Status Register (offset = 4h) [reset = 0h]
- 6.9.6 SHUTDNSRC: PMIC Shut-Down Event Register (offset = 5h) [reset = 0h]
- 6.9.7 BUCK2CTRL: BUCK2 Control Register (offset = 21h) [reset = 50h]
- 6.9.8 BUCK3DECAY: BUCK3 Decay Control Register (offset = 22h) [reset = 70h]
- 6.9.9 BUCK3VID: BUCK3 VID Register (offset = 23h) [reset = 70h]
- 6.9.10 BUCK3SLPCTRL: BUCK3 Sleep Control VID Register (offset = 24h) [reset = 70h]
- 6.9.11 BUCK4CTRL: BUCK4 Control Register (offset = 25h) [reset = Dh]
- 6.9.12 BUCK5CTRL: BUCK5 Control Register (offset = 26h) [reset = Dh]
- 6.9.13 BUCK6CTRL: BUCK6 Control Register (offset = 27h) [reset = Dh]
- 6.9.14 LDOA2CTRL: LDOA2 Control Register (offset = 28h) [reset = Ch]
- 6.9.15 LDOA3CTRL: LDOA3 Control Register (offset = 29h) [reset = 3Ch]
- 6.9.16 DISCHCTRL1: Discharge Control1 Register (offset = 40h) [reset = 55h]
- 6.9.17 DISCHCTRL2: Discharge Control2 Register (offset = 41h) [reset = 55h]
- 6.9.18 DISCHCTRL3: Discharge Control3 Register (offset = 42h) [reset = 15h]
- 6.9.19 PG_DELAY1: Power Good Delay1 Register (offset = 43h) [reset = 0h]
- 6.9.20 FORCESHUTDN: Force Emergency Shutdown Control Register (offset = 91h) [reset = 0h]
- 6.9.21 BUCK2SLPCTRL: BUCK2 Sleep Control Register (offset = 93h) [reset = 50h]
- 6.9.22 BUCK4VID: BUCK4 VID Register (offset = 94h) [reset = 20h]
- 6.9.23 BUCK4SLPVID: BUCK4 Sleep VID Register (offset = 95h) [reset = 20h]
- 6.9.24 BUCK5VID: BUCK5 VID Register (offset = 96h) [reset = 70h]
- 6.9.25 BUCK5SLPVID: BUCK5 Sleep VID Register (offset = 97h) [reset = E8h]
- 6.9.26 BUCK6VID: BUCK6 VID Register (offset = 98h) [reset = E8h]
- 6.9.27 BUCK6SLPVID: BUCK6 Sleep VID Register (offset = 99h) [reset = E8h]
- 6.9.28 LDOA2VID: LDOA2 VID Register (offset = 9Ah) [reset = FFh]
- 6.9.29 LDOA3VID: LDOA3 VID Register (offset = 9Bh) [reset = AAh]
- 6.9.30 BUCK123CTRL: BUCK1-3 Control Register (offset = 9Ch) [reset = 7h]
- 6.9.31 PG_DELAY2: Power Good Delay2 Register (offset = 9Dh) [reset = 21h]
- 6.9.32 SWVTT_DIS: SWVTT Disable Register (offset = 9Fh) [reset = E0h]
- 6.9.33 I2C_RAIL_EN1: VR Pin Enable Override1 Register (offset = A0h) [reset = 80h]
- 6.9.34 I2C_RAIL_EN2/GPOCTRL: VR Pin Enable Override2/GPO Control Register (offset = A1h) [reset = 89h]
- 6.9.35 PWR_FAULT_MASK1: VR Power Fault Mask1 Register (offset = A2h) [reset = C0h]
- 6.9.36 PWR_FAULT_MASK2: VR Power Fault Mask2 Register (offset = A3h) [reset = 3Fh]
- 6.9.37 GPO1PG_CTRL1: GPO1 PG Control1 Register (offset = A4h) [reset = C2h]
- 6.9.38 GPO1PG_CTRL2: GPO1 PG Control2 Register (offset = A5h) [reset = AFh]
- 6.9.39 GPO4PG_CTRL1: GPO4 PG Control1 Register (offset = A6h) [reset = 0h]
- 6.9.40 GPO4PG_CTRL2: GPO4 PG Control2 Register (offset = A7h) [reset = 0h]
- 6.9.41 GPO2PG_CTRL1: GPO2 PG Control1 Register (offset = A8h) [reset = C0h]
- 6.9.42 GPO2PG_CTRL2: GPO2 PG Control2 Register (offset = A9h) [reset = 2Fh]
- 6.9.43 GPO3PG_CTRL1: GPO3 PG Control1 Register (offset = AAh) [reset = 0h]
- 6.9.44 GPO3PG_CTRL2: GPO3 PG Control2 Register (offset = ABh) [reset = 0h]
- 6.9.45 MISCSYSPG Register (offset = ACh) [reset = FFh]
- 6.9.46 LDOA1CTRL: LDOA1 Control Register (offset = AEh) [reset = 7Dh]
- 6.9.47 PG_STATUS1: Power Good Status1 Register (offset = B0h) [reset = 0h]
- 6.9.48 PG_STATUS2: Power Good Status2 Register (offset = B1h) [reset = 0h]
- 6.9.49 PWR_FAULT_STATUS1: Power Fault Status1 Register (offset = B2h) [reset = 0h]
- 6.9.50 PWR_FAULT_STATUS2: Power Fault Status2 Register (offset = B3h) [reset = 0h]
- 6.9.51 TEMPCRIT: Temperature Fault Status Register (offset = B4h) [reset = 0h]
- 6.9.52 TEMPHOT: Temperature Hot Status Register (offset = B5h) [reset = 0h]
- 6.9.53 OC_STATUS: Overcurrent Fault Status Register (offset = B6h) [reset = 0h]
-
7 Applications, Implementation, and Layout
- 7.1 Application Information
- 7.2 Typical Application
- 7.3 Power Supply Coupling and Bulk Capacitors
- 7.4 Dos and Don'ts
- 8 Device and Documentation Support
- 9 Revision History
- 10Mechanical, Packaging, and Orderable Information
封裝選項
請參考 PDF 數據表獲取器件具體的封裝圖。
機械數據 (封裝 | 引腳)
- RSK|64
散熱焊盤機械數據 (封裝 | 引腳)
- RSK|64
訂購信息
6.6.1 Power-Up and Power-Down Sequencing
The power-up and power-down sequence uses the CTL1, CTL4, and CTL5 pins to enable and disable regulators as required by the system. Figure 6-7 shows the sequencing of these enables in a typical power-up and power-down sequence.
A. CTLx are control signals from the
discrete digital from the processor to enable the rails.
B. CTL2 enables SWA1, CTL3 enables
SWB1, and CTL6 enables SWB2. The LDOA2 and LDOA3 enable bits are disabled by
default. The LDOA2_Dis and LDOA3_Dis bits should be set to 1h to enable them.
C. The power fault is masked for 10
ms when the regulator is enabled.
Figure 6-7 Power-Up and Power-Down
SequenceTable 6-6 lists the system power states.
Table 6-6 System Power States
| STATE | GPIO_G3 | EN_S5 | CTL4 | CTL5 |
|---|---|---|---|---|
| G3’ | 1 | 0 | 1 | 0 |
| G3’ | 1 | 1 | 1 | 0 |
| G3 state | 0 | 0 | 0 | 0 |
| S5 state | 0 | 1 | 1 | 1 |