The I²C interface is a 2-wire serial interface. The bus consists of a data line (SDA) and a clock line (SCL) with pullup structures. When the bus is idle, both SDA and SCL lines are pulled high. All the I²C compatible devices connect to the I²C bus through open drain I/O pins, DATA, and CLK. A master device, usually a microcontroller or a digital signal processor, controls the bus. The master is responsible for generating the SCL signal and device addresses. The master also generates specific conditions that indicate the START and STOP of data transfer. A slave device receives data, transmits data, or both on the bus under control of the master device.

The TPS6508700 device works as a slave and supports the following data transfer modes, as defined in the I²C-Bus Specification: standard mode (100 kbps), fast mode (400 kbps), and high-speed mode
(1 Mbps). The interface adds flexibility to the power supply solution, enabling most functions to be programmed to new values depending on the instantaneous application requirements. Register contents are loaded when the V_SYS voltage is higher than V_{SYS_UVLO_5V} and is applied to the TPS6508700 device. The I²C interface is running from an internal oscillator that is automatically enabled when access to the interface is avaialble.

The data transfer protocol for fast and standard modes are exactly the same, therefore, they are referred to as F/S-mode in this document. The protocol for high-speed mode is different from the F/S-mode, and it is referred to as H/S-mode.

The TPS6508700 device supports 7-bit addressing; however, 10-bit addressing and a general call address are not supported. The default device address is 0x5E.