ZHCSFY3B November 2016 – February 2019 TAS2559
PRODUCTION DATA.
請(qǐng)參考 PDF 數(shù)據(jù)表獲取器件具體的封裝圖。
| PARAMETER | STANDARD-MODE | FAST-MODE | UNIT | |||
|---|---|---|---|---|---|---|
| MIN | MAX | MIN | MAX | |||
| fSCL | SCL Clock Frequency | 0 | 100 | 0 | 400 | kHz |
| tHD;STA | Hold Time (repeated) START Condition. After this period, the first clock pulse is generated. | 4 | 0.6 | μs | ||
| tLOW | LOW Period of the SCL Clock | 4.7 | 1.3 | μs | ||
| tHIGH | HIGH Period of the SCL Clock | 4 | 0.6 | μs | ||
| tSU;STA | Setup Time for a Repeated START Condition | 4.7 | 0.6 | μs | ||
| tHD;DAT | Data Hold Time: For I2C Bus Devices | 0 | 3.45 | 0 | 0.9 | μs |
| tSU;DAT | Data Setup Time | 250 | 100 | ns | ||
| tr | SDA and SCL Rise Time | 1000 | 20 + 0.1 × Cb | 300 | ns | |
| tf | SDA and SCL Fall Time | 300 | 20 + 0.1 × Cb | 300 | ns | |
| tSU;STO | Setup Time for STOP Condition | 4 | 0.6 | μs | ||
| tBUF | Bus Free Time Between a STOP and START Condition | 4.7 | 1.3 | μs | ||
| Cb | Capacitive Load for Each Bus Line | 400 | 400 | pF | ||