ZHCSFY3B November 2016 – February 2019 TAS2559
PRODUCTION DATA.
Configures the clock source for BCLK and WCLK
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reserved | ASI1_BCLKS[2:0] | Reserved | ASI1_WCLKS[2:0] | ||||
| RW-0h | RW-0h | RW-0h | RW-0h | ||||
| LEGEND: R/W = Read/Write; R = Read only; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 7 | Reserved | RW | 0h | Reserved |
| 6-4 | ASI1_BCLKS[2:0] | RW | 0h | ASI1 bit clock(BCLK) output source is
0 = ASI1 BDIV divider output 1 = ASI1 DAC clock 2 = Reserved 3 = ASI2 BDIV divider output 4 = ASI2 DAC clock 5=15 = Reserved |
| 3 | Reserved | RW | 0h | Reserved |
| 2-0 | ASI1_WCLKS[2:0] | RW | 0h | ASI1 bit clock(WCLK) output source is
0 = ASI1 WDIV divider output 1 = ASI1 DAC clock 2 = Reserved 3 = ASI2 WDIV divider output 4 = ASI2 DAC clock 5=15 = Reserved |