ZHCSFY3B November 2016 – February 2019 TAS2559
PRODUCTION DATA.
請(qǐng)參考 PDF 數(shù)據(jù)表獲取器件具體的封裝圖。
In DSP mode, the rising edge of the word clock starts the data transfer with the left channel data first and immediately followed by the right channel data. Each data bit is valid on the falling edge of the bit clock.
Figure 32. Timing Diagram for DSP Mode
Figure 33. Timing Diagram for DSP Mode with ASI_OFFSET1=1
Figure 34. Timing Diagram for DSP Mode with ASI_OFFSET1=0 and Inverted Bit Clock For DSP mode, the number of bit-clocks per frame should be greater than twice the programmed word-length of the data. Also the programmed offset value should be less than the number of bit-clocks per frame by at least the programmed word-length of the data.