ZHCSFY3B November 2016 – February 2019 TAS2559
PRODUCTION DATA.
| PARAMETER | IOVDD=1.8V | IOVDD=3.3V | UNIT | ||||
|---|---|---|---|---|---|---|---|
| MIN | MAX | MIN | MAX | ||||
| tH(BCLK) | BCLK High Period | 40 | 30 | ns | |||
| tL(BCLK) | BCLK Low Period | 40 | 30 | ns | |||
| ts(WS) | WCLK setup | 8 | 8 | ns | |||
| th(WS) | WCLK Hold | 8 | 8 | ns | |||
| td(DO-BCLK) | BCLK to DOUT Delay (For LJF Mode Only) | 50% BCLK to 50% DOUT | 35 | 25 | ns | ||
| ts(DI) | DIN Setup | 8 | 8 | ns | |||
| th(DI) | DIN Hold | 8 | 8 | ns | |||
| tr | Rise Time | 10%-90% Rise Time | 8 | 4 | ns | ||
| tf | Fall Time | 90%-10% Fall Time | 8 | 4 | ns | ||
Figure 1. I2C Timing
Figure 2. SPI Interface Timing Diagram
Figure 3. I2S/LJF/RJF Timing in Master Mode
Figure 4. I2S/LJF/RJF Timing in Slave Mode
Figure 5. DSP Timing in Master Mode
Figure 6. DSP Timing in Slave Mode