ZHCSFY3B November 2016 – February 2019 TAS2559
PRODUCTION DATA.
請參考 PDF 數(shù)據(jù)表獲取器件具體的封裝圖。
Configures the CDIV_CLKIN clock input source.
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reserved | CLKOUT_DIN[4:0] | ||||||
| RW-0h | RW-Dh | ||||||
| LEGEND: R/W = Read/Write; R = Read only; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 7-5 | Reserved | RW | 0h | Reserved |
| 4-0 | CLKOUT_DIN[4:0] | RW | Dh | CDIV_CLKIN input is from
0 = GPIO1 1 = GPIO2 2 = GPIO3 3 = GPIO4 4 = GPIO5 5 = GPIO6 6 = GPIO7 7 = GPIO8 8 = GPIO9 9 = GPIO10 10-11 = Reserved 12 = GPI1 13 = GPI2 (Preferred pin usage) 14 = GPI3 15 = PLL_CLK 16 = DAC_MOD_CLK 17 = ADC_MOD_CLK 18 = NDIV_CLK 19-31 = Reserved |