ZHCSFY3B November 2016 – February 2019 TAS2559
PRODUCTION DATA.
請參考 PDF 數(shù)據(jù)表獲取器件具體的封裝圖。
Selects the BDIV clock source
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reserved | ASI2_BDIV_SRC[2:0] | ||||||
| RW-0h | RW-1h | ||||||
| LEGEND: R/W = Read/Write; R = Read only; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 7-3 | Reserved | RW | 0h | Reserved |
| 2-0 | ASI2_BDIV_SRC[2:0] | RW | 1h | ASI1 bit clock divider (BDIV) source is
0 = NDIV_CLK (Generated On-Chip) 1 = DAC_MOD_CLK (Generated On-Chip) 2 = Reserved 3 = ADC_MOD_CLK (Generated On-Chip) 4 = ASI1_DAC_BCLK (at pin) 5 = Reserved 6 = ASI2_DAC_BCLK (at pin) 7 = Reserved |