ZHCSFY3B November 2016 – February 2019 TAS2559
PRODUCTION DATA.
請(qǐng)參考 PDF 數(shù)據(jù)表獲取器件具體的封裝圖。
| PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
|---|---|---|---|---|---|---|
| BOOST CONVERTER | ||||||
| Boost Output Voltage | Average voltage (w/o including ripple) | 8.5 | V | |||
| Boost Converter Switching Frequency | 1.77 | MHz | ||||
| Boost Converter Current Limit | 3 | A | ||||
| Boost Converter Max In-Rush Current | High Efficiency Mode: Max inductor inrush and startup current after enable | 4 | A | |||
| Normal Efficiency Mode: Max inductor inrush and startup current after enable | 1.5 | |||||
| CLASS-D CHANNEL | ||||||
| Output Voltage for Full-Scale Digital Input | 6.6 | VRMS | ||||
| Load Resistance (Load Spec Resistance) | 3.6 | 8 | Ω | |||
| Class-D Frequency | Avg Frequency in Spread-Spectrum Mode | 384 | kHz | |||
| Fixed Frequency | 44.1 × 8 | 48 × 8 | ||||
| Class-D + Boost Efficiency | POUT = 3.5 W (sinewave) ROM Mode 1 | 80 | % | |||
| POUT = 0.5 W (sinewave) ROM Mode 1 | 87 | |||||
| Class-D Output Current Limit (Short Circuit Protection) | VBOOST = 8.5 V, OUT– shorted to VBAT, VBOOST, GND | 6 | A | |||
| Class-D Output Offset Voltage in Digital Input Mode | –2.5 | 2.5 | mV | |||
| Programmable Channel Gain Accuracy | ±0.5 | dB | ||||
| Mute Attenuation | Device in shutdown or device in normal operation and muted | 150 | dB | |||
| VBAT Power Supply Rejection Ratio (PSRR) | Ripple of 200 mVpp at 217 Hz | 110 | dB | |||
| AVDD Power Supply Rejection Ratio (PSRR) | Ripple of 200 mVpp at 217 Hz | 99 | dB | |||
| THD+N | 1 kHz, POUT = 0.1W | 0.0041 | % | |||
| 1 kHz, Po = 0.5W | 0.0036 | |||||
| 1 kHz, Po = 1 W | 0.0035 | |||||
| 1 kHz, Po = 3 W | 0.02 | |||||
| Output Integrated Noise (20Hz-20kHz) - 8 Ω | A-weighted filter, DAC modulator switching | 15.9 | µV | |||
| Signal-to-Noise Ratio | Referenced to 1% THD+N at output, A-weighted | 110.6 | dB | |||
| Max Output Power, 3-A Current Limit | THD+N=1%, 8-Ω Load | 3.7 | W | |||
| THD+N=1%, 6-Ω Load | 4.5 | |||||
| THD+N=1%, 4-Ω Load | 5 | |||||
| Startup Pop | Digital Input, A-weighted output | 10 | mV | |||
| Output Impedance in Shutdown | /RESET = 0 V | 10 | kΩ | |||
| Startup Time | Time taken from end of configuring device in ROM mode1/2 to speaker output signal in SPI mode running at 25 MHz with 48 ksps input | 8 | mS | |||
| Shutdown Time | Measured from time when device is programmed in software shutdown mode | 100 | µS | |||
| CURRENT SENSE | ||||||
| Current Sense Full Scale | Peak current which will give full scale digital output 8-Ω load | 1.25 | APEAK | |||
| Peak current which will give full scale digital output 6-Ω load | 1.48 | |||||
| Peak current which will give full scale digital output 4-Ω load | 1.76 | |||||
| Current Sense Accuracy | IOUT = 354 mARMS (1 W) | 1 | % | |||
| VOLTAGE SENSE | ||||||
| Voltage Sense Full Scale | Peak voltage which will give full scale digital output | 9.353 | VPEAK | |||
| Voltage Sense Accuracy | VOUT = 2.83 Vrms (1 W) | 1 | % | |||
| INTERFACE | ||||||
| Voltage and Current Sense Data Rate | TDM/I2S | 48 | kHz | |||
| Voltage and Current Sense ADC OSR | TDM/I2S | 64 | OSR | |||
| FMCLK | MCLK frequency | 0.512 | 49.15 | MHz | ||
| POWER CONSUMPTION | ||||||
| Power Consumption with Digital Input and Speaker Protection Disabled (ROM MODE 1) | From VBAT, PLL on, no signal | 3 | mA | |||
| From AVDD, PLL on, no signal | 3 | mA | ||||
| From DVDD, PLL on, no signal | 7.2 | mA | ||||
| Power Consumption with Digital Input and Speaker Protection Enabled | From VBAT, PLL on, no signal | 4 | mA | |||
| From AVDD, PLL on, no signal | 5.1 | mA | ||||
| From DVDD, PLL on, no signal | 22 | mA | ||||
| Power Consumption in Hardware Shutdown | From VBAT, /RESET = 0 | 0.1 | µA | |||
| From AVDD, /RESET = 0 | 0.2 | µA | ||||
| From DVDD, /RESET = 0 | 2 | µA | ||||
| Power Consumption in Software Shutdown See Low Power Sleep | From VBAT | 0.1 | µA | |||
| From AVDD | 0.1 | µA | ||||
| From DVDD | 9.7 | µA | ||||
| DIGITAL INPUT / OUTPUT | ||||||
| VIH | High-Level Digital Input Voltage | All digital pins except SDA and SCL, IOVDD = 1.8-V operation | 0.65 × IOVDD | V | ||
| VIL | Low-Level Digital input Voltage | 0.35 × IOVDD | V | |||
| VIH | High-Level Digital Input Voltage | All digital pins except SDA and SCL, IOVDD = 3.3-V operation | 2 | V | ||
| VIL | Low-Level Ddigital Input Voltage | 0.45 | V | |||
| VOH | High-Level Digital Output Voltage | All digital pins except SDA and SCL, IOVDD = 1.8-V operation For IOL = 2 mA and IOH = –2 mA | IOVDD – 0.45 | V | ||
| VOL | Low-Level Digital Output Vvoltage | 0.45 | V | |||
| VOH | High-Level Digital Output Voltage | All digital pins except SDA and SCL, IOVDD = 3.3-V operation For IOL = 2 mA and IOH = –2 mA | 2.4 | V | ||
| VOL | Low-Level Digital Output Voltage | 0.4 | V | |||
| IIH | High-Level Digital Input Leakage Current | Input = IOVDD | –5 | 0.1 | 5 | µA |
| IIL | Low-Level Digital Input Leakage Current | Input = Ground | –5 | 0.1 | 5 | µA |
| MISCELLANEOUS | ||||||
| TTRIP | Thermal Trip Point | 140 | °C | |||