ZHCSFY3B November 2016 – February 2019 TAS2559
PRODUCTION DATA.
請(qǐng)參考 PDF 數(shù)據(jù)表獲取器件具體的封裝圖。
Configures the clock error detection handling
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| DSP_RSTM | Reserved | CE1_SM | CE1_IC | CE2_IC[1:0] | CE1_EN | CE2_EN | |
| RW-0h | RW-0h | RW-0h | RW-0h | RW-0h | RW-0h | RW-0h | |
| LEGEND: R/W = Read/Write; R = Read only; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 7 | DSP_RSTM | RW | 0h | 0 = Reserved |
| 6 | Reserved | RW | 0h | Reserved |
| 5 | CE1_SM | RW | 0h | When clock error1 is detected do soft mute using
0 = hardware mute sequence 1 = DSP mute sequence |
| 4 | CE1_IC | RW | 0h | Clock error detection block 1 input clock is
0 = ASI1 1 = ASI2 |
| 3-2 | CE2_IC[1:0] | RW | 0h | Clock error detection block 2 input clock is
0 = DAC modulator clock 1 = ADC modulator clock 2 = PLL clock 3 = reserved |
| 1 | CE1_EN | RW | 0h | Clock error detection block 1 is
0 = disabled 1 = enabled |
| 0 | CE2_EN | RW | 0h | Clock error detection block 2 is
0 = disabled 1 = enabled |