ZHCSFY3B November 2016 – February 2019 TAS2559
PRODUCTION DATA.
Configures the bit clock pin, timing, and free running mode
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reserved | ASI1_BCLK[3:0] | Reserved | ASI1_BCT | ASI1_FRM | |||
| RW-0h | RW-0h | RW-0h | RW-0h | RW-0h | |||
| LEGEND: R/W = Read/Write; R = Read only; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 7 | Reserved | RW | 0h | Reserved |
| 6-3 | ASI1_BCLK[3:0] | RW | 0h | ASI1 BCLK input is from
0 = GPIO1 (Preferred pin usage) 1 = GPIO2 2 = GPIO3 3 = GPIO4 4 = GPIO5 5 = GPIO6 6 = GPIO7 7 = GPIO8 8 = GPIO9 9 = GPIO10 10-11 = Reserved 12 = GPI1 13 = GPI2 14 = GPI3 15-31 = Reserved |
| 2 | Reserved | RW | 0h | Reserved |
| 1 | ASI1_BCT | RW | 0h | ASI1 BCLK timing as per timing protocol is
0 = normal 1 = inverted |
| 0 | ASI1_FRM | RW | 0h | ASI1 BLCK and WCLK are
0 = active in output modes only when ASI1 is active and codec is powered up 1 = is free-running |