ZHCSFY3B November 2016 – February 2019 TAS2559
PRODUCTION DATA.
請參考 PDF 數(shù)據(jù)表獲取器件具體的封裝圖。
In mono PCM mode, the rising edge of the word clock starts the data transfer of the single channel of data. Each data bit is valid on the falling edge of the bit clock.
Figure 39. Timing Diagram for Mono PCM Mode
Figure 40. Timing Diagram for Mono PCM Mode with ASI_OFFSET1=2
Figure 41. Timing Diagram for Mono PCM Mode with ASI_OFFSET1=2 and Bit Clock Inverted For mono PCM mode, the programmed offset value should be less than the number of bit-clocks per frame by at least the programmed word-length of the data.