ZHCSH28C September 2017 – May 2025 TPA3221
PRODUCTION DATA
If a fault situation occurs while in operation, the device acts accordingly to the fault being a global or a channel fault. A global fault is a chip-wide fault situation and causes all PWM activity of the device to be shut down, and asserts FAULT low. A global fault is a latching fault and clearing FAULT and restarting operation requires resetting the device by toggling RESET. De-asserting RESET should never be allowed with excessive system temperature, so it is advised to monitor RESET with a system microcontroller and only release RESET ( RESET high) if the OTW_CLIP signal is cleared (high). A channel fault results in shutdown of the PWM activity of the affected channel(s). Note that asserting RESET low forces the FAULT signal high, independent of faults being present.
| Fault/Event | Fault/Event Description | Global or Channel | Reporting Method | Latched/Self Clearing | Action needed to Clear | Output FETs |
|---|---|---|---|---|---|---|
| PVDD_X UVP | Voltage Fault | Global | FAULT pin | Self Clearing | Increase affected supply voltage | HI-Z |
| AVDD UVP | ||||||
| POR (AVDD UVP) | Power On Reset | Global | FAULT pin | Self Clearing | Allow AVDD to rise | HI-Z |
| OTW | Thermal Warning | Global | OTW_CLIP pin | Self Clearing | Cool below OTW threshold | Normal operation |
| OTE | Thermal Shutdown | Global | FAULT pin | Latched | Toggle RESET | HI-Z |
| OLP (CB3C>1.7 ms) | OC Shutdown | Channel | FAULT pin | Latched | Toggle RESET | HI-Z |
| CB3C | OC Limiting | Channel | None | Self Clearing | Reduce signal level or remove short | Flip state, cycle by cycle at fs/3 |
| Stuck at Fault(1) | No OSC_IO activity in Peripheral Mode | Global | None | Self Clearing | Resume OSC_IO activity | HI-Z |