ZHCSH28C September 2017 – May 2025 TPA3221
PRODUCTION DATA
- 1
- 1 特性
- 2 應(yīng)用
- 3 說明
- 4 Device Comparison Table
- 5 Pin Configuration and Functions
-
6 Specifications
- 6.1 Absolute Maximum Ratings
- 6.2 ESD Ratings
- 6.3 Recommended Operating Conditions
- 6.4 Thermal Information
- 6.5 Electrical Characteristics
- 6.6 Audio Characteristics (BTL)
- 6.7 Audio Characteristics (PBTL)
- Typical Characteristics, BTL Configuration, AD-mode
- Typical Characteristics, PBTL Configuration, AD-mode
- 7 Parameter Measurement Information
-
8 Detailed Description
- 8.1 Overview
- 8.2 Functional Block Diagrams
- 8.3 Feature Description
- 8.4
Device Functional Modes
- 8.4.1 Powering Up
- 8.4.2 Powering Down
- 8.4.3 Device Reset
- 8.4.4 Device Soft Mute
- 8.4.5
Device Protection System
- 8.4.5.1 Overload and Short Circuit Current Protection
- 8.4.5.2 Signal Clipping and Pulse Injector
- 8.4.5.3 DC Speaker Protection
- 8.4.5.4 Pin-to-Pin Short Circuit Protection (PPSC)
- 8.4.5.5 Overtemperature Protection OTW and OTE
- 8.4.5.6 Undervoltage Protection (UVP) and Power-on Reset (POR)
- 8.4.5.7 Fault Handling
-
9 Application and Implementation
- 9.1 Application Information
- 9.2 Typical Applications
- 9.3 Power Supply Recommendations
- 9.4 Layout
- 10Device and Documentation Support
- 11Revision History
- 12Mechanical, Packaging, and Orderable Information
封裝選項(xiàng)
機(jī)械數(shù)據(jù) (封裝 | 引腳)
- DDV|44
散熱焊盤機(jī)械數(shù)據(jù) (封裝 | 引腳)
- DDV|44
訂購信息
5 Pin Configuration and Functions
The TPA3221 is available in a thermally enhanced TSSOP package.
The package type contains a heat slug that is located on the top side of the device for convenient thermal coupling to the heat sink.
Figure 5-1 DDV PackageHTSSOP 44-Pin(Top View)Table 5-1 Pin Functions
| NAME | NO. | I/O(1) | DESCRIPTION |
|---|---|---|---|
| HEAD | 11 | I | 0 = AD, 1 = HEAD. Refer to: Section 8.3.3 |
| AVDD | 21 | P | AVDD voltage supply. Refer to: Section 8.3.1, Section 9.3.1.2 |
| BST1_M | 43 | P | OUT1_M HS bootstrap supply (BST), 0.033μF capacitor to OUT1_M
required. Refer to: Section 9.2.1.2.3 |
| BST1_P | 44 | P | OUT1_P HS bootstrap supply (BST), 0.033μF capacitor to OUT1_P
required. Refer to: Section 9.2.1.2.3 |
| BST2_M | 23 | P | OUT2_M HS bootstrap supply (BST), 0.033μF capacitor to OUT2_M
required. Refer to: Section 9.2.1.2.3 |
| BST2_P | 24 | P | OUT2_P HS bootstrap supply (BST), 0.033μF capacitor to OUT2_P
required. Refer to: Section 9.2.1.2.3 |
| CMUTE | 17 | P | Mute and Startup Timing Capacitor. Connect a 33nF capacitor to GND. Refer to: Section 8.4.3 |
| FAULT | 4 | O | Shutdown signal, open drain; active low. Refer to: Section 8.3.6 |
| FREQ_ADJ | 14 | O | Oscillator frequency programming pin. Refer to: Section 8.3.4 |
| GAIN/SLV | 2 | I | Closed loop gain and controller/peripheral programming pin. Refer to: Section 8.3.1.1 |
| GND | 5, 6, 7, 18, 19, 20, 25, 26, 33, 34, 41, 42 | P | Ground |
| GVDD | 22 | P | Gate drive supply. Refer to: Section 8.3.1, Section 9.3.1.2 |
| IN1_M | 9 | I | Negative audio input for channel 1 |
| IN1_P | 8 | I | Positive audio input for channel 1 |
| IN2_M | 16 | I | Negative audio input for channel 2 |
| IN2_P | 15 | I | Positive audio input for channel 2 |
| OSCM | 12 | I/O | Oscillator synchronization interface. Refer to: Section 8.3.1.1 |
| OSCP | 13 | I/O | Oscillator synchronization interface. Refer to: Section 8.3.1.1 |
| OTW_CLIP | 3 | O | Clipping warning and Over-temperature warning; open drain; active
low. Refer to: Section 8.3.6 |
| OUT1_M | 35 | O | Negative output for channel 1 |
| OUT1_P | 39, 40 | O | Positive output for channel 1 |
| OUT2_M | 27, 28 | O | Negative output for channel 2 |
| OUT2_P | 32 | O | Positive output for channel 2 |
| PVDD | 29, 30, 31, 36, 37, 38 | P | PVDD supply. Refer to: Section 9.2.1.2.2, Section 9.3.1.3 |
| RESET | 10 | I | Device reset Input; active low. Refer to: Section 8.4.5.7, Section 8.4.1, Section 8.4.2 |
| VDD | 1 | P | Input power supply. Refer to: Section 8.3.1, Section 9.3.1.1 |
| PowerPad? | P | Ground, connect to grounded heatsink. Placed on top side of device. |
(1) I=Input, O=Output, I/O= Input/Output, P=Power
Table 5-2 Mode Selection Pins
| MODE PINS(2) | INPUT MODE(1) | OUTPUT CONFIGURATION | DESCRIPTION | ||||
|---|---|---|---|---|---|---|---|
| IN2_M | IN2_P | HEAD | |||||
| X | X | 0 | 1N/2N + 1 | 2 × BTL | Stereo, BTL output configuration, AD mode modulation | ||
| X | X | 1 | 1N/2N + 1 | 2 × BTL | Stereo, BTL output configuration, HEAD mode modulation | ||
| 0 | 0 | 0 | 1N/2N + 1 | 1 x PBTL | Mono, Parallelled BTL configuration. Connect OUT1_P to OUT2_P and OUT1_M to OUT2_M, AD mode modulation | ||
| 0 | 0 | 1 | 1N/2N + 1 | 1 x PBTL | Mono, Parallelled BTL configuration. Connect OUT1_P to OUT2_P and OUT1_M to OUT2_M, HEAD mode modulation | ||
| 1 | 1 | 0 | 1N/2N + 1 | 1 x BTL | Mono, BTL configuration. OUT1_M and OUT1_P active, AD mode modulation | ||
| 1 | 1 | 1 | 1N/2N + 1 | 1 x BTL | Mono, BTL configuration. OUT1_M and OUT1_P active, HEAD mode modulation | ||
(1) 2N refers to differential input signal, 1N refers to single
ended input signal. +1 refers to number of logic control (
RESET) input pins.
(2) X refers to inputs connected through AC coupling capacitor, 0
refers to logic low (GND), 1 refers to logic high (AVDD).