ZHCSH28C September 2017 – May 2025 TPA3221
PRODUCTION DATA
- 1
- 1 特性
- 2 應用
- 3 說明
- 4 Device Comparison Table
- 5 Pin Configuration and Functions
-
6 Specifications
- 6.1 Absolute Maximum Ratings
- 6.2 ESD Ratings
- 6.3 Recommended Operating Conditions
- 6.4 Thermal Information
- 6.5 Electrical Characteristics
- 6.6 Audio Characteristics (BTL)
- 6.7 Audio Characteristics (PBTL)
- Typical Characteristics, BTL Configuration, AD-mode
- Typical Characteristics, PBTL Configuration, AD-mode
- 7 Parameter Measurement Information
-
8 Detailed Description
- 8.1 Overview
- 8.2 Functional Block Diagrams
- 8.3 Feature Description
- 8.4
Device Functional Modes
- 8.4.1 Powering Up
- 8.4.2 Powering Down
- 8.4.3 Device Reset
- 8.4.4 Device Soft Mute
- 8.4.5
Device Protection System
- 8.4.5.1 Overload and Short Circuit Current Protection
- 8.4.5.2 Signal Clipping and Pulse Injector
- 8.4.5.3 DC Speaker Protection
- 8.4.5.4 Pin-to-Pin Short Circuit Protection (PPSC)
- 8.4.5.5 Overtemperature Protection OTW and OTE
- 8.4.5.6 Undervoltage Protection (UVP) and Power-on Reset (POR)
- 8.4.5.7 Fault Handling
-
9 Application and Implementation
- 9.1 Application Information
- 9.2 Typical Applications
- 9.3 Power Supply Recommendations
- 9.4 Layout
- 10Device and Documentation Support
- 11Revision History
- 12Mechanical, Packaging, and Orderable Information
9.4.2.2 PBTL (Outputs Paralleled before LC filter) Application Printed Circuit Board Layout Example
A. Note: PCB layout example shows composite layout.
Dark grey: Top layer copper traces, light gray: Bottom layer copper traces. All
PCB area not used for traces are GND copper pour (transparent on example
image)
B. Note T1: PVDD decoupling bulk capacitors
are as close as possible to the PVDD and GND_X pins, the heat sink sets the
distance. Wide traces are routed on the top layer with direct connection to the
pins and without going through vias. No vias or traces are blocking the current
path.
C. Note T2: Close decoupling of PVDD with low impedance X7R ceramic capacitors is placed under the heat sink and close to the pins.
D. Note T3: Heat sink needs to have a good connection to PCB ground.
Figure 9-5 PBTL (Outputs Paralleled before LC filter) Application Printed Circuit Board - Composite