ZHCSH28C September 2017 – May 2025 TPA3221
PRODUCTION DATA
| MIN | TYP | MAX | UNIT | |||
|---|---|---|---|---|---|---|
| PVDD | Power-stage supply | DC supply voltage | 7 | 30 | 32 | V |
| VDD(1) | Supply voltage for internal LDO regulator to supply GVDD and AVDD | DC supply voltage | 7 | 32 | V | |
| External supply for VDD, GVDD and AVDD. Internal LDO bypassed | DC supply voltage | 4.5 | 5 | 5.5 | V | |
| AVDD | Supply voltage for analog circuits | DC supply voltage | 4.5 | 5 | 5.5 | V |
| GVDD | Supply voltage for gate-drive circuitry | DC supply voltage | 4.5 | 5 | 5.5 | V |
| LOUT(BTL) | Output filter inductance | Minimum output inductance at IOC | 5 | 10 | μH | |
| LOUT(PBTL) | Output filter inductance, PBTL before the LC filter | Minimum output inductance at IOC | 5 | 10 | ||
| Output filter inductance, PBTL after the LC filter | Minimum output inductance at half IOC , each inductor | 5 | 10 | |||
| FPWM | PWM frame rate selectable for AM interference avoidance; 1% Resistor tolerance | Nominal | 575 | 600 | 625 | kHz |
| AM1 | 510 | 533 | 555 | |||
| AM2 | 460 | 480 | 500 | |||
| R(FREQ_ADJ) | PWM frame rate programming resistor | Nominal; Controller mode | 49.5 | 50 | 50.5 | k? |
| AM1; Controller mode | 29.7 | 30 | 30.3 | |||
| AM2; Controller mode | 9.9 | 10 | 10.1 | |||
| CPVDD | PVDD close decoupling capacitors | 1.0 | μF | |||
| V(FREQ_ADJ) | Voltage on FREQ_ADJ pin for peripheral mode operation | Peripheral Mode (Connect to AVDD) | 5 | V | ||