ZHCSH28C September 2017 – May 2025 TPA3221
PRODUCTION DATA
| PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
|---|---|---|---|---|---|---|
INTERNAL VOLTAGE REGULATOR AND CURRENT CONSUMPTION | ||||||
| AVDD | Voltage regulator. Only used as reference node when supplied by internal LDO. Voltage regulator bypassed for VDD = 5V. | VDD = 30V | 5 | V | ||
| IVDD | VDD supply current. LDO mode (VDD > 7V) | Operating, no audio signal | 25 | mA | ||
| Reset mode | 118 | μA | ||||
| VDD supply current. LDO bypass mode (VDD = 5V) | Operating, no audio signal | 150 | ||||
| Reset mode | 50 | |||||
| IAVDD | Gate-supply current. LDO bypass mode (VDD = 5V) | Operating, no audio signal | 10 | mA | ||
| Reset mode | 1 | |||||
| IGVDD | Gate-supply current. LDO bypass mode (VDD = 5V), AD-mode modulation | 50% duty cycle | 16 | |||
| Reset mode | 50 | μA | ||||
| Gate-supply current. LDO bypass mode (VDD = 5V), HEAD-mode modulation | HEAD-mode modulation | 16 | mA | |||
| Reset mode | 50 | μA | ||||
| IPVDD | Total PVDD idle current, AD-mode modulation, BTL | 50% duty cycle with recommended output filter | 15 | mA | ||
| 50% duty cycle with recommended output filter, TC = 25 °C | 13 | |||||
| Reset mode, No switching | 1 | |||||
| Total PVDD idle current, HEAD-mode modulation, BTL | HEAD-mode modulation with recommended output filter | 10 | ||||
| HEAD-mode with recommended output filter, TC = 25 °C | 9 | |||||
| Reset mode, No switching | 1 | |||||
| ANALOG INPUTS | ||||||
| VIN | Maximum input voltage swing | ±2.8 | V | |||
| IIN | Maximum input current | -1 | 1 | mA | ||
| G | Inverting voltage Gain, VOUT/VIN(Controller Mode) | R1 = 5.6kΩ, R2 = OPEN | 18 | dB | ||
| R1 = 20kΩ, R2 = 100kΩ | 24 | |||||
| R1 = 39kΩ, R2 = 100kΩ | 30 | |||||
| R1 = 47kΩ, R2 = 75kΩ | 34 | |||||
| Inverting voltage Gain, VOUT/VIN(Peripheral Mode) | R1 = 51kΩ, R2 = 51kΩ | 18 | ||||
| R1 = 75kΩ, R2 = 47kΩ | 24 | |||||
| R1 = 100kΩ, R2 = 39kΩ | 30 | |||||
| R1 = 100kΩ, R2 = 16kΩ | 34 | |||||
| RIN | Input resistance | G = 18dB | 48 | k? | ||
| G = 24dB | 24 | |||||
| G = 30dB | 12 | |||||
| G = 34dB | 7.7 | |||||
| OSCILLATOR | ||||||
| fOSC(IO)(1) | Nominal, Controller Mode | FPWM × 6 | 3.45 | 3.6 | 3.75 | MHz |
| AM1, Controller Mode | 3.06 | 3.198 | 3.33 | |||
| AM2, Controller Mode | 2.76 | 2.88 | 3 | |||
| VIH | High level input voltage | 1.88 | V | |||
| VIL | Low level input voltage | 1.65 | V | |||
| EXTERNAL OSCILLATOR (Peripheral Mode) | ||||||
| fOSC(IO) | CLK input on OSCM/OSCP (Peripheral Mode) | 2.3 | 3.78 | MHz | ||
OUTPUT-STAGE MOSFETs | ||||||
| RDS(on) | Drain-to-source resistance, low side (LS) | TJ =
25 °C, Excludes metallization resistance, GVDD = 5V | 70 | m? | ||
| Drain-to-source resistance, high side (HS) | 70 | m? | ||||
| I/O PROTECTION | ||||||
| Vuvp,AVDD | Undervoltage protection limit, AVDD | 4 | V | |||
| Vuvp,AVDD,hyst(2) | Undervoltage protection hysteresis, AVDD | 0.1 | V | |||
| Vuvp,PVDD | Undervoltage protection limit, PVDD_x | 6.4 | V | |||
| Vuvp,PVDD,hyst(2) | Undervoltage protection hysteresis, PVDD_x | 0.45 | V | |||
| OTW | Overtemperature warning, OTW_CLIP(2) | 115 | 125 | 135 | °C | |
| OTWhyst(2) | Temperature drop needed below OTW temperature for OTW_CLIP to be inactive after OTW event. | 20 | °C | |||
| OTE(2) | Overtemperature error | 145 | 155 | 165 | °C | |
| OTEhyst(2) | A reset needs to occur for FAULT to be released following an OTE event | 20 | °C | |||
| OTE-OTW(differential)(2) | OTE-OTW differential | 25 | °C | |||
| OLPC | Overload protection counter | fPWM = 600kHz (1024 PWM cycles) | 1.7 | ms | ||
| IOC, BTL | Overcurrent limit protection, speaker output current | Nominal peak current in 1? load | 10 | A | ||
| IOC, PBTL | 20 | A | ||||
| IDCspkr, BTL | DC Speaker Protection Current Threshold | BTL current imbalance threshold | 1.8 | A | ||
| IDCspkr, PBTL | PBTL current imbalance threshold | 3.6 | A | |||
| IOCT | Overcurrent response time | Time from switching transition to flip-state induced by overcurrent. | 150 | ns | ||
| IPD | Output pulldown current of each half | Connected when RESET is active to provide bootstrap charge. Not used in SE mode. | 3 | mA | ||
| STATIC DIGITAL SPECIFICATIONS | ||||||
| VIH | High level input voltage | HEAD, OSCM, OSCP, CMUTE, RESET | 1.9 | V | ||
| VIL | Low level input voltage | 0.8 | V | |||
| Ilkg | Input leakage current | 100 | μA | |||
| OTW/SHUTDOWN (FAULT) | ||||||
| RINT_PU | Internal pullup resistance, OTW_CLIP to AVDD, FAULT to AVDD | 20 | 26 | 32 | k? | |
| VOH | High level output voltage | Internal pullup resistor | 3 | 3.3 | 3.6 | V |
| VOL | Low level output voltage | IO = 4mA | 200 | 500 | mV | |
| Device fanout | OTW_CLIP, FAULT | No external pullup | 30 | devices | ||