ZHCSH28C September 2017 – May 2025 TPA3221
PRODUCTION DATA
VDD can be connected to PVDD in systems using only a single power supply. VDD is connected to an internal LDO that is then used to supply AVDD and GVDD for digital and analog circuits as well as to supply the gate drive.
To reduce device power consumption, the internal LDO can be bypassed by connecting VDD, AVDD and GVDD to an external 5 V power supply.
Proper connection, routing, and decoupling techniques are highlighted in the TPA3221 device EVM User's Guide (as well as the Section 9.1 section and Section 9.4.2 section) and must be followed as closely as possible for proper operation and performance. Deviation from the guidance offered in the TPA3221 device EVM User's Guide, which followed the same techniques as those shown in the Section 9.1 section, may result in reduced performance, errant functionality, or even damage to the TPA3221 device. To simplify the power supply requirements for the system, the TPA3221 device includes a integrated low-dropout (LDO) linear regulator to create a 5V rail for AVDD and GVDD supplies. The linear regulator is internally connected to the VDD supply and its output is present on the AVDD pin, providing a connection point for an external bypass capacitors. It is important to note that the linear regulator integrated in the device has only been designed to support the current requirements of the internal circuitry, and should not be used to power any additional external circuitry. Additional loading on these pins could cause the voltage to sag and increase noise injection, which negatively affects the performance and operation of the device.