SPRZ398K November 2012 – September 2024 DRA745 , DRA746 , DRA750 , DRA756
Multiple Resets Required Before Chip Is Functional
High
Multiple resets (up to three) are needed after the initial PORz reset before the device is fully functional and allow cores to connect via emulation debugger. The resets can be cold (PORz) or warm (RESETn) pin resets, or emulation system resets issued from the debugger.
After initial PORz deassertion, wait at least 2.5ms and then issue a second and a third reset at least 2.5ms apart (either PORz or RESETn pin assertions at least 2.5ms duration or emulation system resets from the debugger).
SR 1.0
TDA2x: 1.0
DRA75x, DRA74x: 1.0
AM572x: 1.0