SPRZ398K November 2012 – September 2024 DRA745 , DRA746 , DRA750 , DRA756
HSDIVIDER1 CLKOUT4 Could Glitch During On-the-Fly Divider Change to/from Divide-by-2.5
Low
When HSDIVIDER1/2 CLKOUT4 (CM_DIV_H14_DPLL_PER/CM_DIV_H24_DPLL_CORE[5:0] DIVHS) configuration is changed between an odd divide value and divide-by-2.5 setting, the clock output could glitch. This could result in unexpected behavior of the peripheral receiving the clock. This case impacts GPU clock.
To avoid glitch, the user can always change first to/from an even divider setting, such as divide-by-4, before reconfiguring to divide-by-2.5 or from divide-by-2.5 to an odd divider.
Sequence to switch HSDIVIDER1/2 CLKOUT4 from any odd divider to divide-by-2.5:
Sequence to switch HSDIVIDER1/2 CLKOUT4 from divide-by-2.5 to any odd divider:
SR 2.0, 1.1, 1.0
TDA2x: 2.0, 1.1, 1.0
DRA75x, DRA74x: 2.0, 1.1, 1.0
AM572x: 2.0, 1.1