SPRZ398K November 2012 – September 2024 DRA745 , DRA746 , DRA750 , DRA756
PCIe Unaligned Read Access Issue
Medium
Access to the PCIe slave port that are not 32-bit aligned will result in incorrect mapping to TLP Address and Byte enable fields. Therefore, byte and half-word accesses are not possible to byte offset 0x1, 0x2, or 0x3.
To workaround this issue, there are two options:
SR 2.0, 1.1, 1.0
TDA2x: 2.0, 1.1, 1.0
DRA75x, DRA74x: 2.0, 1.1, 1.0
AM572x: 2.0, 1.1