CRITICALITY

High

DESCRIPTION

For ECC-enabled DDR regions, only full quanta aligned writes are allowed (16-b quanta for 16-b data bus, and 32-b quanta for 32-b data bus). The EMIF has a mechanism to detect illegal sub-quanta writes to ECC-enabled space. It has two methods of reporting such errors. In case of such an illegal write:

1. An error interrupt will be generated to the CPU.
2. The EMIF will give an error status response to the offending initiator on the internal bus.

In some corner conditions the internal bus response (method #2 above) may become corrupted and give a false read or write error response in spite of all transactions in the EMIF command fifo being valid/legal. Depending on how each initiator handles the specific internal bus error response, this can result in system instability. For instance, a false error response on an MPU read may result in an abort.

The error interrupt behavior (method #1 above) is always correct. No false error interrupts are created, and only true illegal writes to ECC space are reported via interrupt. Access type and initiator for the last offending access will be logged.

WORKAROUND

Disable ECC.

OR

Enable ECC for desired ranges in EMIF1, and ensure that all DDR write accesses to all of EMIF1 (including ECC protected and unprotected ranges) from all initiators are a multiple of quanta size and are quanta aligned.

EMIF2 (which doesn't support ECC) can support arbitrarily aligned accesses.

REVISIONS IMPACTED

SR 1.1, 1.0

TDA2x: 1.1, 1.0

DRA75x, DRA74x: 1.1, 1.0

AM572x: 1.1