SPRZ398K November 2012 – September 2024 DRA745 , DRA746 , DRA750 , DRA756
PCIe Unintentional Translation of Outbound Message TLPs
Medium
There is a limitation in internal address translation unit in which unintentional translation of outbound message TLPs can occur if the third and fourth double words of the header match an iATU region. The unintentional translation is most likely to occur in the case of an address translation region at location 0x0 in address space since many message TLPs require the third and fourth double words of the header to be 0x0.
Outbound completion TLPs also partially suffer from the same issue. Completion TLPs are never translated by the controller. However if the client address is held at a value which matches an outbound iATU region when a completion TLP is being transmitted, the controller will reduce the credit counter of the type specified in that region. Because the client address bus is normally held at address 0x0 when transmitting completion TLPs, this issue generally occurs when an address translation region is defined at address 0x0.
Do not configure an outbound iATU region starting at address 0x0. Instead, only configure outbound iATU regions starting at address 0x1000 or greater.
At the SoC level, this workaround effectively reduces each PCIE_SSx 256MiB L3_MAIN address window to 256MiB – 4KB, starting at address 0x2000_1000 for PCIE_SS1 and address 0x3000_1000 for PCIE_SS2.
SR 2.0, 1.1, 1.0
TDA2x: 2.0, 1.1, 1.0
DRA75x, DRA74x: 2.0, 1.1, 1.0
AM572x: 2.0, 1.1