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SPRZ398K November 2012 – September 2024 DRA745 , DRA746 , DRA750 , DRA756

1
1Introduction
1. Related Documentation
2. Trademarks
3. Modules Impacted
2Silicon Advisories
1. Revisions SR 2.0, 1.1, 1.0 - Advisories List
2. i202
3. i378
4. i631
5. i694
6. i698
7. i699
8. i727
9. i729
10. i734
11. i767
12. i782
13. i783
14. i802
15. i803
16. i807
17. i808
18. i809
19. i810
20. i813
21. i814
22. i815
23. i818
24. i819
25. i820
26. i824
27. i826
28. i829
29. i834
30. i837
31. i840
32. i841
33. i842
34. i843
35. i847
36. i849
37. i852
38. i854
39. i855
40. i856
41. i859
42. i861
43. i862
44. i863
45. i868
46. i869
47. i870
48. i871
49. i872
50. i874
51. i875
52. i878
53. i879
54. i880
55. i881
56. i882
57. i883
58. i884
59. i887
60. i889
61. i890
62. i893
63. i895
64. i896
65. i897
66. i898
67. i899
68. i900
69. i901
70. i903
71. i916
72. i927
73. i929
74. i930
75. i932
76. i933
77. i936
78. i940
79. i2446
3Silicon Limitations
1. Revisions SR 2.0, 1.1, 1.0 - Limitations List
2. i596
3. i641
4. i833
5. i838
6. i844
7. i845
8. i848
9. i850
10. i851
11. i853
12. i857
13. i858
14. i876
15. i877
16. i892
17. i909
4Silicon Cautions
1. Revisions SR 2.0, 1.1, 1.0 - Cautions List
2. i781
3. 4.1 107
4. i827
5. i832
6. i836
7. i839
8. i864
9. i885
10. i886
11. i912
12. i926
13. i931
14. i935
5Revision History

i699

DMA4 Channel Fails to Continue With Descriptor Load When Pause Bit Is Cleared

CRITICALITY

Low

DESCRIPTION

This Bug can occur only in a channel that is part of a channel chain. If channel chaining is not used, this bug is never seen.

An exact corner case sequence of events must occur. The sequence is:

The channel is enabled and then aborted*.
This same channel is now configured as part of a channel chain (it should not be the head of the channel chain).
The channel is configured as "software synchronized" or "hardware synchronized at destination with prefetch enabled"
The channel gets enabled through linking.

* Following is the subset of abort conditions for this scenario:

The channel is disabled in the middle of transaction and channnel is not a drain candidate.
The channel gets a transaction error on write port but not at the end-of-block transaction.
The channel gets a read transaction error and is not a drain candidate.

WORKAROUND

The software workaround is to configure DMA4 to be in no-standby or force-standby mode before clearing the PAUSE bit. The DMA4 can be reverted back to smart-standby mode after a certain period (after detecting DMA4_CSRi[15:15] of corresponding channel to be 0 or ensuring DMA4_CSRi[7:7] bit of corresponding channel to be 0. This ensures descriptor load completion or channel termination.

REVISIONS IMPACTED

SR 2.0, 1.1, 1.0

TDA2x: 2.0, 1.1, 1.0

DRA75x, DRA74x: 2.0, 1.1, 1.0

AM572x: 2.0, 1.1