SPRZ398K November 2012 – September 2024 DRA745 , DRA746 , DRA750 , DRA756
MMCHS DCRC Errors During Tuning Procedure
Low
In UHS=I mode, the SD bus operates in high clock frequency mode and the data windows from card on CMD and DAT lines get smaller. The position of the data windows varies depending on the card and the host system. To adjust the sampling clock when SDR104/HS200 operation mode is used the MMC/SDIO host controller supports a tuning procedure. This tuning circuit is a dedicated DLL which delays the clock signal used, for data sampling.
DCRC error interrupts (MMCHS_STAT[21] DCRC=0x1) can occur during the tuning procedure.
As explained in SD Host Controller Spec version 3.00 Feb 18, 2010, the controller is supposed to inhibit all interrupts except BRR (block read ready) during the tuning procedure (ET=1).
Some DCRC interrupts occur from time to time during tuning upon CMD19 (send tuning block).
This DCRC interrupt, occurs when the last tuning block fails (the last ratio tested).
The root cause is that the delay from CRC check until the interrupt is asserted is bigger than the delay until assertion of the tuning end flag (which masks the interrupts); therefor, when the interrupt bit toggles, the tuning has already ended.
After the DCRC interrupt occurs during the tuning procedure, software should clear the interrupt before the next command is sent: (MMCHS_STAT[21] DCRC=0x1).
Another workaround is to disable DCDR interrupt during the tuning procedure:
MMCHS_IE [21] DCRC_ENABLE is set to 0x0 (masked).
SR 2.0, 1.1, 1.0
TDA2x: 2.0, 1.1, 1.0
DRA75x, DRA74x: 2.0, 1.1, 1.0
AM572x: 2.0, 1.1