SPRZ398K November 2012 – September 2024 DRA745 , DRA746 , DRA750 , DRA756
DLL SW Reset Bit Does Not Reset to 0 after Execution
Medium
When autoidle is enabled (MMCHS_SYSCONFIG[0] AUTOIDLE=0x1), clock gets cut off and the reset completion signal would not be recorded by the processor. Hence, though the reset executed and finished, the MMCHS_DLL[31] DLL_SOFT_RESET flag will remain asserted indefinitely and another soft reset will be ignored.
Disable autoidle (MMCHS_SYSCONFIG[0] AUTOIDLE=0x0), before DLL reset and re-enable autoidle after the reset.
Set MMCHS_SYSCONFIG[0] AUTOIDLE = 0 before reset
Set MMCHS_SYSCONFIG[0] AUTOIDLE = 1 after the reset
SR 2.0, 1.1, 1.0
TDA2x: 2.0, 1.1, 1.0
DRA75x, DRA74x: 2.0, 1.1, 1.0
AM572x: 2.0, 1.1