SLVSHR0 May 2025 TPS2HCS08-Q1
PRODUCTION DATA
The output voltage ramps while the load capacitance is being charged. During this period, the power dissipation in the FET is high due to the large drain-to-source voltage. The power dissipation and the resultant increase in the silicon junction temperature limits the capacitance that can be charged before the device hits thermal shutdown. In general, lower the charging rate (current), the higher the value of capacitance that can be charged. But if a lower charging current is used, the charging time will be higher. In the application cases considered here, it is expected that the FET junction temperature will not reach the thermal shutdown threshold.